P1076 July 21, 2016 Meeting Minutes

Attendees:

Peter Flake, Lieven Lemiengre, Jim Lewis, Brent Hayhoe, Patrick Lehmann, Kevin Jennings, Rob Gaddi

Restarting with item 64
64 WaitLevel - enhancement priority 63
65 NamedPkgbody in 2016_MeetingMay5 is covered by abstract packages - hence reject
66 UnionsVariants enhancement
67 ExpressionsInBitStringLiterals enhancement
68 RequireResolution - enhancement
- assert not (1 fs = 0 sec) report "time of 1 fs is not representable" severity failure ; -- should work
- LRM needs clarified, implementations seem ok
- See LRM 5.2.4.2 - 2nd half of 2nd paragraph
- See P 275 Note 3
- Sense - language should always truncate to 0 if the value is not representable
- also see https://github.com/VLSI-EDA/PoC/blob/master/src/common/physical.vhdl#L210-L219
69 RelaxedOthersAggregate enhancement
70 RecordMemberAttribute file under "Converting Things", However, without any form of polymorphism it is difficult.
71 BidirectionalConnections interfaces
72 OptionalSemicolon regularization
73 FunctionKnowsVectorSize enhancement
74 CrossLanguageInstances some day maybe
75 StdulogicResolution some day maybe - scary changing something that may remotely have an impact
76 RelatedRecords Interfaces
77 UniqueCondition reject
78 SynthesizableReportsAssertions reject
79 NaturalVector some day maybe
80 PackageNameCase regularization
81 DeferredSharedVariables enhancement
82 ImplicitConversionNumeric Integer
83 EmptyRecord regularization
84 ArchitectureGeneric Someday maybe -- comment: consider with improved configurations
Restart at 85

Rob, Lieven

Topic revision: r3 - 2020-02-17 - 15:36:16 - JimLewis