P1076 August 20, 2015 Meeting Minutes

Attendees:

• Jim Lewis, Brent Hayhone, Ernst Christen, Rob Gaddi, Ryan Hinton

Agenda:

Meeting Discussion

• Review Interface Use Modelsstarting at InterfaceAndBundleEnhancements
• Model for Transaction Based Testbench
• RTL Bundles
  • RTL designers will likely need something like a variant bundle
  • Alternately variant bundle I1 could be an internconnect instance
  • Multiple slaves on an I2C bus
  • SystemVerilog examples about ModPort
  • What happens when a user needs to migrate from a regular bundle to a variant bundle?
  • 1 solution vs 2 solutions: Are 2 necessary?
• RTL Design, Subprogram usage, and Hardware Creation
  • In SV, when an imported subprogram is called in an interface, where does the hardware get created
  • How do we transition from SystemLevel modeling with subprograms to implementation
  • Communication between Behavioral Design w/ RTL Design
  • Discussion of Generic Memory Interface: ReadMemMaster, WriteMemMaster, ReadMemSlave, WriteMemSlave
    • Initially no details of interface
    • Over time interface is refined to be a particular RAM type: Static, ..., DDR3
  • Within a bundle, is a subprogram called with method notation or package like subprogram notation.
  • Do we need abstract bundles? vs Determination at Bundle instance time.
• Ryan: Key think from bundle is connectivity of plumbing.
• Current capability with records
• Things reflected upon for VHDL-2008 revision
• Make generic packages not fully analyzed
  • Defer analysis until instantiation.
  • Make few restrictions on generic types:
    • IE: allow indexing within generic package and fail when analyzing package instance.
    • How does this impact generic packages being passed?

Review and Approve Meeting Minutes:

• Rob and Brent

Next Meeting: Thursday August 27, 11 am Pacific

Previous Meeting: Thursday August 6, 2015