Subject: [vhdl-200x] Boolean Equivalence
From: Bailey, Stephen (SBailey@model.com)
Date: Fri Dec 19 2003 - 16:20:39 PST
Based on Tim's recent post, would the people that have been arguing against the implicit Boolean conversion support the following (which is based on our discussions of how to exploit don't cares in case statements):
Current if, while, etc. condition contexts remain unchanged.
We define in the language derivatives of each of these, call them:
if?
while?
when?
until?
etc.
The idea is that the same expected capability is provided, but these constructs use whatever COND operator is visible to implicitly convert the top level expression into a boolean type.
This makes it even more explicit that you want an implicit conversion to boolean to be applied (the conversion would still need to be declared and visible). There should be no danger of unexpected use of the implicit conversion.
Would this make the proposal acceptable?
------------
Stephen Bailey
TME, Mentor Graphic's Model Technology Group
sbailey@model.com
303-775-1655 (mobile, preferred)
720-494-1202 (office)
www.model.com
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