Subject: Re: [vhdl-200x] Boolean Equivalence
From: Evan Lavelle (anti.spam1@dsl.pipex.com)
Date: Mon Dec 22 2003 - 03:16:45 PST
Bailey, Stephen wrote:
> Based on Tim's recent post, would the people that have been arguing
> against the implicit Boolean conversion support the following (which
> is based on our discussions of how to exploit don't cares in case
> statements):
>
> Current if, while, etc. condition contexts remain unchanged.
>
> We define in the language derivatives of each of these, call them:
>
> if?
> while?
> when?
> until?
> etc.
This has the merit that it's completley backwards-compatible and that
the meaning of existing code couldn't be changed depending on package
visibility. It also has the merit that anyone who chooses to use these
new statements knows in advance what the implications are and so they,
rather than the language, can be blamed for any problems.
But, instead of adding another half-a-dozen or whatever statements, why
not just add one new first-class datatype, which already has a defined
mapping between logic values and 'true' and 'false'? This also has the
two merits described above, as well as allowing the existing syntax for
'if', 'while', etc., and the other advantages I mentioned in the "An
alternative proposal to boolean equivalence" (I'd link it, but eda.org
seems to be down again).
Evan Lavelle
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