Subject: Re: [vhdl-200x] An alternative proposal to boolean equivalence
From: Munden Rick (Rick.Munden@Siemens.com)
Date: Fri Dec 19 2003 - 19:59:35 PST
Steve,
I don't think people are trying to say anything that is like verilog is
bad. I think their point is we have two languages that are different.
They (can) serve different needs. We can build using stone or stucco.
Which is better? It depends on our needs. Stone lasts longer but is
more expensive and slower. Often, we only need to build for the short
term. Why would we want to use stone? Other times we want to build for
the long term. The extra time and expense is justified. Then we use
stone.
For the work I do, which is not synthesis, a restrictive, verbose,
strongly typed language is ideal. That is not the case for everyone and
thats OK. That is why, at the end of the so called language wars, there
were still two languages.
My understanding is that the boolean equivalence issue came up because
of PSL. I would like to understand that issue better. What are the
requirements and is there another approach to meeting them? I have not
had time to look this up on the website. Is there something there to study?
Thanks,
Rick
Bailey, Stephen wrote:
>>Equality is trickier: do you want to handle don't cares? Is that a
>>proposal? It could be handled in the same way as the
>>case(x/z) statement
>>when the operands are of type 'logic', but this would be incompatible
>>with Verilog. Not a problem, but it would be nice to be compatible.
>
>
> Yes, there will be a proposal on how to handle don't care. But, we'll discuss that when it is ready.
>
> It is nice to see that when the context changes, Verilog is now something to be emulated. Point being: let's stop using Verilog as an ad hominem attack against proposals. Judge the proposals on their merits.
>
> Thanks,
>
> -Steve Bailey
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