Subject: RE: [vhdl-200x] An alternative proposal to boolean equivalence
From: Bailey, Stephen (SBailey@model.com)
Date: Fri Dec 19 2003 - 13:20:14 PST
> Equality is trickier: do you want to handle don't cares? Is that a
> proposal? It could be handled in the same way as the
> case(x/z) statement
> when the operands are of type 'logic', but this would be incompatible
> with Verilog. Not a problem, but it would be nice to be compatible.
Yes, there will be a proposal on how to handle don't care. But, we'll discuss that when it is ready.
It is nice to see that when the context changes, Verilog is now something to be emulated. Point being: let's stop using Verilog as an ad hominem attack against proposals. Judge the proposals on their merits.
Thanks,
-Steve Bailey
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