Subject: RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003
From: Bailey, Stephen (SBailey@model.com)
Date: Fri Dec 19 2003 - 13:14:52 PST
This is the essence of the difference in opinion.
> -----Original Message-----
> 1) if we ...
> 2) if we = '1' ...
> (2) is a plain and simple logic error; brain fade. No tool can be
> expected to protect against this; the designer just got it
> wrong. That's
> what simulation is for.
> (1) is completely different. If the language is strongly
> typed, then the
> compiler *knows* that the user made an error. If we add an implicit
> COND, however, then the compiler doesn't know, and the user may never
> find out.
I disagree that this is completely different. A logic error is a logic error no matter the form. The compiler never knows that the user made a logic error in case 1. You are inferring the error is a logic error based on your own interpretation of the boolean equivalence of std_ulogic. (Thanks as that makes the point that there is a well understood/agreed to equivalence.) The only thing the compiler is telling you is that the expression is not boolean. It is not telling you that the logic level is wrong. Naming conventions are used to help the human infer such logic errors. If anything, the code snippets imply the code is right because there's no indication that the logic level is supposed to be 0! (BTW, if the user may never find out about the error in 1, the same applies to 2 as the error is identical.)
The crux of the disagreement is whether
if sl = '1' then (if sl = '0' then)
Is inherently better at identifying logic errors than
if sl then (if not sl then)
when neither naming conventions nor comments provide any clue as to what the active logic level is. I fail to see any inherent advantage for one form over the other.
> Our job is to ensure that the designer gets as much help as possible
> from the compiler. Surely we can't throw out type safety just because
> compilers can't find logical errors? This would be throwing
> out the baby
> with the bathwater.
Please refrain from sweeping assessments. The proposal is limited in context and has no impact on strong typing in any other context. We disagree to the impact to strong typing within this context.
Life is full of trade-offs. Is there significant tangible benefit to justify the cost? We have offered to make the use of this capability explicit (allow those who don't like it, to opt out -- with opting out the default). Is that not satisfactory?
In summary, what is more important:
1. Decreased typing and
2. Ability to be consistent in the treatment of condition contexts between PSL and VHDL.
Satisfying some group of people's subjective assessment that one form is inherently superior to the other in human detection of logic errors.
I prefer tangible, objective benefits over subjective benefits, especially when they are optional as it satisfies the greatest number of people.
BTW, Happy Holidays to everyone!
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