Subject: RE: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g
From: Bailey, Stephen (SBailey@model.com)
Date: Fri Dec 19 2003 - 16:13:55 PST
PSL defines boolean equivalence for std_ulogic. From the 1.01 version of the PSL LRM:
"3.1.20 False: An interpretation of certain values of certain data types in an HDL.
In the Verilog flavor, the single bit value 1'b0 is interpreted as the logical value False.
"In the VHDL flavor, the values STD.Standard.Boolean'(False), STD.Standard.Bit'('0'), and IEEE.std_logic_1164.std_logic'('0') are all interpreted as the logical value False.
"In the GDL flavor, the Boolean value 'false' and bit value 0B are both interpreted as the logical value
False.
"3.1.52 True: An interpretation of certain values of certain data types in an HDL.
In the Verilog flavor, the single bit value 1'b1 is interpreted as the logical value True.
"In the VHDL flavor, the values STD.Standard.Boolean'(True), STD.Standard.Bit'('1'), and IEEE.std_logic_1164.std_logic'('1') are all interpreted as the logical value True.
"In the GDL flavor, the Boolean value 'true' and bit value 1B are both interpreted as the logical value True.
"5.1 HDL expressions
A Boolean HDL expression, shown in Box 11 [this is the syntax productions], is any HDL expression that the HDL allows to be used as the condition of an if statement."
NOTES:
1. I added some formatting (vertical white space) to increase readability.
2. Ben Cohen has written in an earlier post that he has a proposal to modify the 1.1 LRM currently being written to include the meta-logic values of std_ulogic in the definition of false.
3. For those who may not be aware:
- Boolean expressions are the fundamental building block of sequences and properties (that is, they are prevalent throughout a PSL specification).
- There are tools today (Safelogic, NC, ModelSim, others) that already support VHDL-flavor of PSL.
- You can embed PSL inside the HDL and include arbitrary HDL within your PSL sections. (Again, the tools already support this.)
PSL does not require COND as they have already defined a boolean equivalence. VHDL needs the COND proposal to be consistent with PSL and to improve language efficiency in expression (or whatever you wish to call "typing efficiency").
-Steve Bailey
> -----Original Message-----
> From: owner-vhdl-200x@eda.org
> [mailto:owner-vhdl-200x@eda.org]On Behalf
> Of Hamish Moffatt
> Sent: Friday, December 19, 2003 4:30 PM
> To: 'vhdl-200x@eda.org'
> Subject: Re: [vhdl-200x] Implicit conversion, Overloading, & Strong
> Typin g
>
>
> Bailey, Stephen wrote:
> > - Do nothing to address an enhancement request that is elevated in
> > priority due to the desire to incorporate PSL as the property
> > specification capability in VHDL. (I already pointed out
> the obvious
> > language inconsistencies that arise if we do nothing.)
>
> Why is the COND operator required for PSL?
>
>
> Hamish
>
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