Subject: RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003
From: Bailey, Stephen (SBailey@model.com)
Date: Fri Dec 19 2003 - 15:57:18 PST
> > 2. Ability to be consistent in the
> > treatment of condition contexts between PSL and VHDL.
> ...
> Your #2 is based on the assumption that implicit boolean
> conversion is
> appropriate in the PSL context, and therefore for consistency
> should be
> allowed in all VHDL condition contexts. Why is implicit boolean
> conversion appropriate in PSL though?
Actually, it is much simpler than that. The designers of PSL decided this was desired and it is already provided in PSL. The inconsistency exists today.
> At a guess it would seem just to reduce typing again; thus everything
> collapses to simply reduced typing. I don't find much merit in that
> personally.
I was not part of the PSL decision making process. Therefore, I cannot say why they did what they did. I have the same assumptions as you, but am not troubled by it.
> > I prefer tangible, objective benefits over subjective benefits,
> > especially when they are optional as it satisfies the
> greatest number
> > of people.
>
> As do I. I feel that better compile-time checking is worth a bit more
> typing.
As pointed out twice already, there is no compile-time checking that prevents logic errors. If we make it optional (must explicitly use the capability), then you retain today's compile time checks that the expression is boolean.
-Steve Bailey
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