Subject: [vhdl-200x] A 2nd proposal to boolean equivalence
From: Tim Davis (timdavis@aspenlogic.com)
Date: Fri Dec 19 2003 - 15:52:35 PST
Summary:
1) Permit non-static case statement expressions
2) Implement an overloadable "?" selector operator.
3) Implement the enumerated type declaration with my type value
equivalence syntax. (Specified in early message last week)
Rationale:
How can we augment VHDL's primary syntax and semantic strengths -- in a
general way -- to make it easier for people to use it in domain specific
ways? What test should be applied to any proposal to see if strengthens
VHDL?
As an example consider operator overloading. This syntax and semantic
concept gave VHDL a very general purpose way to allow domain specific
operators to be "built-into" the syntax of the language. 1164 would not
have survived if using the type system it constructed meant having to
live with
and(and(a,b),c)
rather than
a and b and c
IE the ability to have packages and enumerated types wasn't enough. It
was operator overloading that made the general purpose jump that
associated "and" with and(). It facilitated the package developer's
ability to provide a great solution.
So, by extrapolation, I think what people might be looking for is a way
to "overload" the if-then-else statement. (We have overloaded names,
overloaded operators, overloaded functions, why not overloaded
statements?) I suspect that might be a little tough to put together
syntactically.
Or, put another way, how do we make a general purpose extension to the
if-then-else statement to make it non-type specific? To answer this
question you have to look no further then the case statement (selector).
The if-then-else is nothing but a **boolean type** specific selector. We
don't need it at all really. You could write perfectly reasonable models
with the case statement alone based on any type. The "if" statement is
so engrained in our casual (english) speech that we forget that it is a
selector with no real connection to boolean conditional expressions. The
syntax provides an implicit association between true and the first set
of statements followed by false and the second set of statements. The
mapping is arbitrary and has nothing to do with boolean values or logic!
The choice to make logic implementations active high or active low
re-enforces that idea. The if-elsif-endif construct is just nested case
statements.
Unfortunately, VHDL makes this hard on us by requiring the selector
expression to be static. Lets remove that requirement. While the use of
case statements in place of if statements may seem unpalitable to some I
would do it in a heartbeat. Absolutely no confusion over
positive/negative logic would be a windfall.
Second, lets add the boolean selector operator "?" which many languages
have now and permit it to be overloaded. Then the vast majority of logic
operations which utilize the if-then-else now have an overloadable
expression syntax to fall back on. That would only be a 50% solution.
The if-then-else gathers multiple independent statements under one roof.
Third, (as I proposed before) utilize enumerated type declarations with
explicit type equivalency built into the declaration. Here is the syntax
I proposed:
type negative_logic is ('0' => true, '1'=>false, 'Z'=>false, 'X'=>false)
with boolean,
('0'=>1, '1'=>0, 'Z'=>-1, 'X'=>-1)
with integer,
('0' => "0", '1'=>"1", 'Z'=>"Z", 'X'
=> "X") with string;
Now if the analyzer sees an IF with a non-boolean type it can check the
unexpected type for a translation mapping and apply that transparently.
The advantage is that the mapping is explicitly present in a package or
the user's code thus documenting the intention directly.
-- Aspen Logic, Inc. By: Tim Davis, President
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