Subject: Re: [vhdl-200x] Implicit conversion, Overloading, & Strong Typing
From: Evan Lavelle (eml@riverside-machines.com)
Date: Thu Dec 18 2003 - 14:12:51 PST
Jim Lewis wrote:
> Hi,
> I think we need to put this in perspective.
>
> We allow overloading and overloading is good.
>
> I think mainly the VHDL community is not comfortable
> with the thought of "implicit conversions".
>
> The implicit conversions do nothing more than overloading
> a conditional expression to accept the types for which
> the implicit COND operator is defined.
Hang on. You can't overload an expression; that doesn't make sense. You
want to change the type of an expression according to its context.
> It should not have been called "user defined". It will
> be an overloadable operator that is added to the language.
Ok, the issue is that you want to add an invisible operator into the
language, and that operator is overloaded. This isn't an overloading
issue; its an issue of whether it makes sense to have invisible (or
implicit, or whatever you want to call it) operators hiding at various
points in the language.
I can't personally see any justification for this; I would like someone
to come up with a reasoned academic argument for it, rather than a
utilitarian argument.
And, on the subject of the utilitarian/keystroke argument, it's well
known that a total of two people in the Verilog community make an awful
lot of noise about keystroke counts, and neither of them does
verification. One of them does training, and the other does
implementation (not that I have any problem with that). It's time to get
some perspective here. An 'average' chip, if it exists, might take from
5 to 100 man years to specify, design, code, document, verify, and
implement. How much of this 5 - 100 man years is taking up with typing
on a keyboard? Forget it; it's *zero*.
Evan Lavelle
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