Subject: [vhdl-200x] Implicit conversion, Overloading, & Strong Typing
From: Jim Lewis (Jim@synthworks.com)
Date: Thu Dec 18 2003 - 12:03:49 PST
Hi,
I think we need to put this in perspective.
We allow overloading and overloading is good.
I think mainly the VHDL community is not comfortable
with the thought of "implicit conversions".
The implicit conversions do nothing more than overloading
a conditional expression to accept the types for which
the implicit COND operator is defined.
It should not have been called "user defined". It will
be an overloadable operator that is added to the language.
All of the overloading must be explicitly created and
will more than likely only be done for the types in the
standard packages. It may even end up being limited
to only bit and std_ulogic. It may also include
integers, bit_vector, std_ulogic_vector, std_logic_vector,
signed and unsigned.
My expectation even though it is called user defined is
that it will only be defined by standard packages.
Again, this is overloading and as such it is not
something that ruins strong typing.
I have to admit, I did not like implicit boolean overloading
at first. I did not think we could get a good enough
proposal together to make it work in a clean manner.
With the overloading of binary logic operators,
I think we have a good, clean solution. When you look
at the power of what we have, I think you will like it.
I also think it is going to be quite powerful.
We are moving the Cheese some. Hence, it will take
some getting used to. In reality, I don't think
either of the two read any differently:
if nCs = '0' then
if not nCs then
It is simply a matter of how you visually check for
polarity. In the first case it is '0'. In the second
case it is "not".
Cheers,
Jim
Steve Casselman wrote:
> I think the fear with implicit conversion is that the compiler will try to
> figure out what the programmer _might_ have wanted. VHDL enforces "what you
> see is what you get" I'm for keeping it that way. It goes with the turf.
>
> Steve
>
>
>>In other words, the compiler has to
>>do the work to figure out what the programmer wanted.
>
>
>
>
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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