Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose De...
From: Tim Schneider (Tim.Schneider@synopsys.com)
Date: Thu Dec 18 2003 - 13:00:28 PST
At 06:10 PM 12/17/2003, VhdlCohen@aol.com (and others) wrote:
>BEN: There might be a problem with that in that many sysnthesis vendors
>ignore the sensitivity list and assume that the process is sensitive to
>all signals read by the process. That why current tools may give a
>warning, but will synthesize a process with no sensitivity list.
>... How many times have we forgotten to either add or verify that the list
>is complete?
>If that is the case, the above process will use clk as a "latch enable".
>This gets back to the issue of compatibility between RTL simulation vs
>gate-level simulation of synhesized outputs.
Most all EDA tools either give warning or errors on this.. it's up
to the user to pay attention to their log files IMHO.
Design Compiler always gives a warning message on this code.. also
the SNPS simulator VCSMX does the same (provided you enable synth.
policy checks)
Formality (formal equiv. checker) also flags these as errors (unless you
override
with an env. variable.. then they become merely warnings ;-)
Finally the LEDA rtl rule checker flags this when running code through
several of the rulesets. (synth or simulation)
-tim
Tim Schneider
Synopsys, Inc.
Mesa, AZ
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