Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose De...
From: VhdlCohen@aol.com
Date: Wed Dec 17 2003 - 17:10:44 PST
Inline comments:
n a message dated 12/17/2003 3:47:42 PM Pacific Standard Time,
SBailey@model.com writes:
Note that we have no plans on tabling this proposal. There have been no
technical problems found with the proposal. The proposal is one of several issues
needed to facilitate the incorporation of PSL as the property specification
and temporal assertion capability in VHDL.
BEN: PSL already assumes '1' to be equivalent to true, and anything else is
false.
I am in the process of clarifying for PSL 1.1 that TRUE for '1' and 'H' only
and FALSE for anything else.
The complaints have all come down to subjectivity as to whether
if sl then
is more readable than
if sl = '1' then
For those who like the latter, they are free to continue using it. For those
who see nothing wrong with the former and appreciate the fact that it is
quicker to write, they can use it.
Ben: I like the if sl then ...
When only "clk" is in the sensitivity list (and there is no subordinance to
another if clause, i.e. reset), many synthesizers will accept the following
for a clock edge specification, and it will simulate correctly, assuming no weak
or metavalues are involved (a shortcoming to every method but rising_edge()
and falling_edge().)
main: process (clk)
begin
if clk = '1' then -- means rising edge clock
do_rising_edge_stuff(inputs, outputs);
end if;
end prodess;
BEN: There might be a problem with that in that many sysnthesis vendors
ignore the sensitivity list and assume that the process is sensitive to all signals
read by the process. That why current tools may give a warning, but will
synthesize a process with no sensitivity list.
... How many times have we forgotten to either add or verify that the list is
complete?
If that is the case, the above process will use clk as a "latch enable".
This gets back to the issue of compatibility between RTL simulation vs
gate-level simulation of synhesized outputs.
Ben Cohen
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