Subject: RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose De...
From: Bailey, Stephen (SBailey@model.com)
Date: Wed Dec 17 2003 - 17:38:19 PST
Quick comment below.
When only "clk" is in the sensitivity list (and there is no subordinance to another if clause, i.e. reset), many synthesizers will accept the following for a clock edge specification, and it will simulate correctly, assuming no weak or metavalues are involved (a shortcoming to every method but rising_edge() and falling_edge().)
main: process (clk)
begin
if clk = '1' then -- means rising edge clock
do_rising_edge_stuff(inputs, outputs);
end if;
end prodess;
BEN: There might be a problem with that in that many sysnthesis vendors ignore the sensitivity list and assume that the process is sensitive to all signals read by the process. That why current tools may give a warning, but will synthesize a process with no sensitivity list.
... How many times have we forgotten to either add or verify that the list is complete?
If that is the case, the above process will use clk as a "latch enable".
This gets back to the issue of compatibility between RTL simulation vs gate-level simulation of synhesized outputs.
I just note that this issue with synthesis tools has nothing to do with the proposal. It exists currently and would presumably continue to exist after any language change.
-Steve Bailey
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