Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,S an Jose Dec 4, 2003
From: Marcus Harnisch (marcus_harnisch@mint-tech.com)
Date: Thu Dec 18 2003 - 11:18:27 PST
Rick,
Rick Munden writes:
> Matthias,
>
> You make a good point. Some argue that if you don't like a new feature
> you don't have to use it. I find that most of the code I work with was
> originally written by someone else. How do I restrict their usage of a
> new feature that makes code maintenance more difficult?
Provided that we (actually just those of us who can vote) agree on
keeping the boolean conversion operators in separate packages[1],
which I personally consider a great idea, you just grep for the
package name. If you can't find it, you can be sure that nobody is
using it. If nobody is referencing the package the code won't even
compile.
A more elegant approach would involve a changed library mapping, so
that references to the offending package would be resolved to an empty
package you created just for linting the code. If the code still
compiles, you're fine.
Isn't VHDL just great? You can do all these things relatively easy.
Overloading the logical operators to accept one boolean input makes
sense to me, since it is -- when spec'ed out right -- a well defined
process. This is very different from implicit conversion of inputs to
expressions, which I was afraid of initially!
By overloading these operators, you actually ensure
consistency. Compare that to an arbitrary number of attempts to model
the behavior manually with only a few people getting it right. Now
there is an ongoing debate (language independent) whether overloading
in general has been a good idea in the first place. But that is beyond
the scope of our discussion. In special cases, where manual modelling
is needed, you can still do it.
I'm just, again, concerned about the mnemonic names and propose that
to_boolean() will be provided as a minimum (possibly together with
appropriate operators) in order to maintain a consistent pattern of
type conversion function names in VHDL.[2]
Best regards,
Marcus
Footnotes:
[1] Except the one that takes a boolean argument and simply returns
that same value. That way conditions could always implicitly call
the conversion operator without having to test the type first.
[2] Type conversion functions traditionally have been composed of the
name of the target type with a `to_' prefix. With the notable
exception of `to_stdlogic(vector)' :-( Thus my resistance
against any mnemonic form of to_string().
"Was it to_str(), to_strng(), to_st(), to_stg(), or to_stng()?
Darn, I need to look it up again! Well, at least I was able to
save some key strokes."
-- Marcus Harnisch | Mint Technology, a division of LSI Logic marcus_harnisch@mint-tech.com | 200 West Street, Waltham, MA 02431 Tel: +1-781-768-0772 | http://www.lsilogic.com
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