Subject: Re: [vhdl-200x] Should we merge 1164 into 1076?
From: Swart, Chuck (cswart@model.com)
Date: Thu Dec 18 2003 - 13:31:31 PST
I think that there is another important reason for merging 1164 into 1076:
If we do so, then 1076 can directly exploit the intended semantics of
1164, just
as we currently do with STANDARD and TEXTIO packages.
For example "-" for std_logic can be interpreted as a don't care in
case statements.
I'm not particularly in favor of merging the two packages, but, if we
do, we might
as well take full advantage of the combined semantics.
Chuck Swart
Peter Ashenden wrote:
>Dear colleagues,
>
>[Disclaimer: I am speaking here as a WG member, not as DASC Chair.]
>
>From time to time, it has been suggested that we merge the standard logic
>package definitions into the base VHDL standard document. I would like to
>see if there is currently interest in doing so.
>
>The reasons for doing so are:
>
>(1) The standard logic types are so widely used in VHDL modeling now that
>they have become an integral part of the language and its environment.
>
>(2) Maintaining the standards separately is an administrative and logistical
>burden. In particular, ensuring that revisions are synchronized is
>difficult. Since most of the people involved in P1164 are also actively
>involved in P1076, they could work as a functional team of P1076 with less
>overhead.
>
>Reasons agains are:
>
>(3) Adding the standard logic types to P1076 would mean all VHDL tools would
>have to provide them, whereas now, a tool vendor could decide not to
>implement them and still be compliant with 1076.
>
>(4) If you merge 1164 into 1076, do you then do 1076.2? And 1076.3?
>1076.4? Where does it stop?
>
>Comments?
>
>Cheers,
>
>PA
>
>--
>Dr. Peter J. Ashenden peter@ashenden.com.au
>Ashenden Designs Pty. Ltd. www.ashenden.com.au
>PO Box 640 Ph: +61 8 8339 7532
>Stirling, SA 5152 Fax: +61 8 8339 2616
>Australia Mobile: +61 414 70 9106
>
>
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