Subject: Re: [vhdl-200x] Implicit conversion
From: Hamish Moffatt (hamish_moffatt@agilent.com)
Date: Thu Dec 18 2003 - 15:00:41 PST
Steve Casselman wrote:
> I think the fear with implicit conversion is that the compiler will try to
> figure out what the programmer _might_ have wanted. VHDL enforces "what you
> see is what you get" I'm for keeping it that way. It goes with the turf.
I agree. If I write
if we_n then
instead of
if we_n = '0' then
by mistake, I'd rather find out at compile time than simulation time (or
perhaps in the lab or at a customer site months later). VHDL's ability
to find errors at compile time is a great benefit and I'm opposed to
anything that weakens that. The readability benefit just isn't big
enough for me, if it even exists at all.
Hamish
-- Hamish Moffatt R&D Engineer Data Networks Division Agilent Technologies +61 3 9210 5782 (T210 5782) Tel
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