Re: [vhdl-200x] Implicit conversion

Subject: Re: [vhdl-200x] Implicit conversion
From: Jim Lewis (
Date: Thu Dec 18 2003 - 16:44:40 PST

Hamish Moffatt wrote:

> I agree. If I write
> if we_n then
> instead of
> if we_n = '0' then
> by mistake, I'd rather find out at compile time than simulation time

I don't buy this argument. I think if you write:

    if we_n then instead of: if not we_n then

then you are just as likely to write:

    if we_n = '1' then instead of: if we_n = '0' then

Either way, if you don't verify your design well enough,
well, then you get what you get.

> VHDL's ability to find errors at compile time is a great
> benefit and I'm opposed to anything that weakens that.
I agree, but I don't really think this weakens anything.

I personally was very annoyed about IEEE 1164 picking a
resolved type as the defacto type rather than picking
an unresolved type (std_ulogic/std_ulogic_vector) and
using the resolved type only for tristates.
In fact, I would change this if I could justify it, but
this will never happen as it would break too much code.
Note backwards compatibility is a big requirement of
the VHDL-200X effort.


Jim Lewis
Director of Training   
SynthWorks Design Inc. 

Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

This archive was generated by hypermail 2b28 : Thu Dec 18 2003 - 16:46:01 PST