Subject: [sv-ac] syntax: compatibility with verilog and other issues
From: Cindy Eisner (EISNER@il.ibm.com)
Date: Thu Feb 06 2003 - 04:01:02 PST
all,
i would like to raise the issue of syntactical compatibility with verilog.
i find the introduction of vhdl-like keywords "and", "or", etc. very
jarring. therefore, i propose that
1. proposal: move to more verilog-like syntax: "&" for "and", "|" for
"or", etc.
also, i would like to see a short-hand for a sequential implication in
which the right-hand side starts a cycle after the left-hand side
completes. today, we have:
(a;b;c) => (d;e;f)
which means that if we see a followed by b followed by c, then we should
see d followed by e followed by f, and d must happen the cycle of c. to
say something similar, but where (d;e;f) starts the cycle *after* c, we
must today say:
(a;b;c) => (true;d;e;f)
if we eliminate the "true", as some have requested, then we have to say
(a;b;c) => (1;d;e;f)
or use a leading delay. i think that a delay of one is a very common
situation, and would like to see a short-cut syntax for it. in psl we
have:
|-> sequence implication where right-hand side starts the cycle the
left-hand side ends
|=> sequence implication where right-hand side starts the cycle after the
left-hand side ends
i would like to see a similar idea in sv. therefore, i propose that
2. proposal: add a sequence implication operator which requires the
right-hand side to start a cycle after the left-hand side
note that i have not specificed a syntax. of course, i prefer "|->" and "
|=>" as in psl.
regards,
cindy.
Cindy Eisner
Formal Methods Group Tel: +972-4-8296-266
IBM Haifa Research Laboratory Fax: +972-4-8296-114
Haifa 31905, Israel e-mail:
eisner@il.ibm.com
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