Subject: Re: [sv-ac] syntax: compatibility with verilog and other issues
From: Cindy Eisner (EISNER@il.ibm.com)
Date: Thu Feb 13 2003 - 00:14:24 PST
surrendra,
>The problem with using & for sequence is that it always requires you to
>have sequence delineation, other than parenthesis, regardless of whether
>the operands are boolean or sequences.
yes, but my point is that i think that requiring delineation of a sequence
is a good thing, regardless of whether or not it is required for parsing.
cindy.
Cindy Eisner
Formal Methods Group Tel: +972-4-8296-266
IBM Haifa Research Laboratory Fax: +972-4-8296-114
Haifa 31905, Israel e-mail:
eisner@il.ibm.com
"dudani@us04.synopsys.com" <Surrendra.Dudani@synopsys.com>@eda.org on
10/02/2003 17:36:33
Sent by: owner-sv-ac@eda.org
To: sv-ac@eda.org
cc:
Subject: Re: [sv-ac] syntax: compatibility with verilog and other issues
The problem with using & for sequence is that it always requires you to
have sequence delineation, other than parenthesis, regardless of whether
the operands are boolean or sequences. For example,
When "and" is used for sequence conjunction, expression "a and b" means a
sequence, irrespective of whether a and b are boolean or sequences
themselves. And, use parenthesis to form a sub-expression (a and b)
When & is used as a sequence conjunction and {} for sequence delineation,
one would need to use {a} & {b} , And, use parenthesis to form a
sub-expression ({a} & {b})
Overall, more typing and levels of delineations than "and", "or"
Surrendra
At 02:28 PM 2/9/2003 +0200, you wrote:
>adam,
>
> >To allow & to mean both "bitwise and" and "sequence and" you will need
>context
> >delineation to disambiguate them. I.e.
>.
>.
>.
> >Is it sufficient (visually and logically) to use parenthesis?
>
>good question. i think that in any case, parentheses will be required
>around a sequence in order to get the thing to be parseable with an LR1
>(yacc-like) parser. hopefully that is the intent. i was surprised to
hear
>someone say in the last meeting that parentheses were not required around
>the use of a sequence. i hadn't noticed that. therefore, i propose the
>following:
>
>proposal a: the grammar should be parseable by an LR1 (yacc-like) parser.
>
>proposal b: parentheses should be required around the use of a sequence
>(other than concatentation).
>
>as i said, i believe that "b" is needed in order to achieve "a". "a" is
>the important goal.
>
>that leaves us with "visually". yes, i believe that visually, parentheses
>are enough. it is the same as the interpretation of arithmetic operators
>being determined by the type of the operands in verilog.
>
>regards,
>
>cindy.
>
>Cindy Eisner
>Formal Methods Group Tel: +972-4-8296-266
>IBM Haifa Research Laboratory Fax: +972-4-8296-114
>Haifa 31905, Israel e-mail:
>eisner@il.ibm.com
>
>
>Adam Krolnik <krolnik@lsil.com> on 06/02/2003 18:17:58
>
>To: Cindy Eisner/Haifa/IBM@IBMIL
>cc: sv-ac@eda.org
>Subject: Re: [sv-ac] syntax: compatibility with verilog and other
issues
>
>
>
>
>
>Good evening Cindy;
>
> >1. proposal: move to more verilog-like syntax: "&" for "and", "|"
for
> >"or", etc.
>
>To allow & to mean both "bitwise and" and "sequence and" you will need
>context
>delineation to disambiguate them. I.e.
>
> {b} & {c;d}
>
>is different than
>
> b & c;d
>
>
>Is it sufficient (visually and logically) to use parenthesis?
>
>b & (c;d)
>
>(b) & (c;d)
>
>
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive
Suite 300
Marlboro, MA 01752
Tel: 508-263-8072
Fax: 508-263-8123
email: dudani@synopsys.com
**********************************************
This archive was generated by hypermail 2b28 : Thu Feb 13 2003 - 00:11:33 PST