Subject: Re: [sv-ac] syntax: compatibility with verilog and other issues
From: Cindy Eisner (EISNER@il.ibm.com)
Date: Mon Feb 17 2003 - 00:39:03 PST
shalom,
>Actually, "or" is also used for "or" gate primitives.
yes. thanks.
cindy.
Cindy Eisner
Formal Methods Group Tel: +972-4-8296-266
IBM Haifa Research Laboratory Fax: +972-4-8296-114
Haifa 31905, Israel e-mail:
eisner@il.ibm.com
Shalom.Bresticker@motorola.com on 15/02/2003 19:23:33
To: Cindy Eisner/Haifa/IBM@IBMIL
cc: Kevin Cameron x3251 <Kevin.Cameron@nsc.com>, sv-ac@eda.org
Subject: Re: [sv-ac] syntax: compatibility with verilog and other issues
Actually, "or" is also used for "or" gate primitives.
> definition 1 of consistent: the current use of "or" in verilog is only
for
> event expressions, therefore consistency demands keeping it so.
Shalom
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