Subject: Re: [sv-ac] syntax: compatibility with verilog and other issues
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Feb 10 2003 - 09:16:06 PST
> From: "Cindy Eisner" <EISNER@il.ibm.com>
>
> kevin,
>
> >> 1. proposal: move to more verilog-like syntax: "&" for "and", "|" for
> >> "or", etc.
> >
> >'or' is already there for event expressions.
>
> yes, but in my mind an event expression is an entirely different animal.
>
I was just saying the use of "and" had been suggested elsewhere.
> >The EC did have a short
> >discussion about adding other operators -
> >
> > http://www.eda-twiki.org/sv-ec/hm/0386.html (follow thread)
> >
> >I think the EC is waiting to see if the AC covered this kind of thing to
> >avoid having different syntax for event expressions/sequences.
>
> not sure what you mean here. i didn't follow the whole thread you point to
> above, but mike mcnamara seemed to make a very strong point that allowing
> "and" as an event control wouldn't make a lot of sense. can you explain
> exactly what decision the ec is waiting on, and what the implications are?
"and" makes sense if you are using "persistent" events (normal events don't
overlap).
I don't think the EC is waiting on any particular decision, it would just
be nice to have consistent syntax.
> >IMO it's easier for users if you use different operators for event
> >expressions WRT reading other peoples code.
>
> yes, i agree. i think that event expressions are very different than
> logical expressions, and the syntax of the language should make a strong
> distinction between them.
>
> cindy.
Kev.
> Cindy Eisner
> Formal Methods Group Tel: +972-4-8296-266
> IBM Haifa Research Laboratory Fax: +972-4-8296-114
> Haifa 31905, Israel e-mail:
> eisner@il.ibm.com
>
>
> "Kevin Cameron x3251" <Kevin.Cameron@nsc.com> on 06/02/2003 19:45:09
>
> To: sv-ac@eda.org, Cindy Eisner/Haifa/IBM@IBMIL
> cc:
> Subject: Re: [sv-ac] syntax: compatibility with verilog and other issues
>
>
>
> > From: "Cindy Eisner" <EISNER@il.ibm.com>
> >
> >
> > all,
> >
> > i would like to raise the issue of syntactical compatibility with
> verilog.
> > i find the introduction of vhdl-like keywords "and", "or", etc. very
> > jarring. therefore, i propose that
> >
> > 1. proposal: move to more verilog-like syntax: "&" for "and", "|" for
> > "or", etc.
>
> 'or' is already there for event expressions. The EC did have a short
> discussion about adding other operators -
>
> http://www.eda-twiki.org/sv-ec/hm/0386.html (follow thread)
>
> I think the EC is waiting to see if the AC covered this kind of thing to
> avoid having different syntax for event expressions/sequences.
>
> IMO it's easier for users if you use different operators for event
> expressions WRT reading other peoples code.
>
> Kev.
>
> > also, i would like to see a short-hand for a sequential implication in
> > which the right-hand side starts a cycle after the left-hand side
> > completes. today, we have:
> >
> > (a;b;c) => (d;e;f)
> >
> > which means that if we see a followed by b followed by c, then we should
> > see d followed by e followed by f, and d must happen the cycle of c. to
> > say something similar, but where (d;e;f) starts the cycle *after* c, we
> > must today say:
> >
> > (a;b;c) => (true;d;e;f)
> >
> > if we eliminate the "true", as some have requested, then we have to say
> >
> > (a;b;c) => (1;d;e;f)
> >
> > or use a leading delay. i think that a delay of one is a very common
> > situation, and would like to see a short-cut syntax for it. in psl we
> > have:
> >
> > |-> sequence implication where right-hand side starts the cycle the
> > left-hand side ends
> > |=> sequence implication where right-hand side starts the cycle after the
> > left-hand side ends
> >
> > i would like to see a similar idea in sv. therefore, i propose that
> >
> > 2. proposal: add a sequence implication operator which requires the
> > right-hand side to start a cycle after the left-hand side
> >
> > note that i have not specificed a syntax. of course, i prefer "|->" and
> "
> > |=>" as in psl.
> >
> > regards,
> >
> > cindy.
> >
> > Cindy Eisner
> > Formal Methods Group Tel: +972-4-8296-266
> > IBM Haifa Research Laboratory Fax: +972-4-8296-114
> > Haifa 31905, Israel e-mail:
> > eisner@il.ibm.com
> >
> >
> >
>
>
>
>
>
>
>
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