Subject: Re: [sv-ac] syntax: compatibility with verilog and other issues
From: Cindy Eisner (EISNER@il.ibm.com)
Date: Sun Feb 09 2003 - 04:28:19 PST
adam,
>To allow & to mean both "bitwise and" and "sequence and" you will need
context
>delineation to disambiguate them. I.e.
.
.
.
>Is it sufficient (visually and logically) to use parenthesis?
good question. i think that in any case, parentheses will be required
around a sequence in order to get the thing to be parseable with an LR1
(yacc-like) parser. hopefully that is the intent. i was surprised to hear
someone say in the last meeting that parentheses were not required around
the use of a sequence. i hadn't noticed that. therefore, i propose the
following:
proposal a: the grammar should be parseable by an LR1 (yacc-like) parser.
proposal b: parentheses should be required around the use of a sequence
(other than concatentation).
as i said, i believe that "b" is needed in order to achieve "a". "a" is
the important goal.
that leaves us with "visually". yes, i believe that visually, parentheses
are enough. it is the same as the interpretation of arithmetic operators
being determined by the type of the operands in verilog.
regards,
cindy.
Cindy Eisner
Formal Methods Group Tel: +972-4-8296-266
IBM Haifa Research Laboratory Fax: +972-4-8296-114
Haifa 31905, Israel e-mail:
eisner@il.ibm.com
Adam Krolnik <krolnik@lsil.com> on 06/02/2003 18:17:58
To: Cindy Eisner/Haifa/IBM@IBMIL
cc: sv-ac@eda.org
Subject: Re: [sv-ac] syntax: compatibility with verilog and other issues
Good evening Cindy;
>1. proposal: move to more verilog-like syntax: "&" for "and", "|" for
>"or", etc.
To allow & to mean both "bitwise and" and "sequence and" you will need
context
delineation to disambiguate them. I.e.
{b} & {c;d}
is different than
b & c;d
Is it sufficient (visually and logically) to use parenthesis?
b & (c;d)
(b) & (c;d)
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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