Re: [sv-ac] syntax: compatibility with verilog and other issues

Subject: Re: [sv-ac] syntax: compatibility with verilog and other issues
From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Feb 06 2003 - 08:17:58 PST

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Good evening Cindy;

>1. proposal: move to more verilog-like syntax: "&" for "and", "|" for
>"or", etc.

To allow & to mean both "bitwise and" and "sequence and" you will need context
delineation to disambiguate them. I.e.

   {b} & {c;d}

is different than

   b & c;d

Is it sufficient (visually and logically) to use parenthesis?

b & (c;d)

(b) & (c;d)

     Adam Krolnik
     Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074

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