TWiki>
VerilogAMS Web>AmsDiscussionDoc>DiscreteAnalogModelingInSV (2011-05-17, KevinCameron)EditAttach
VerilogAMS Web>AmsDiscussionDoc>DiscreteAnalogModelingInSV (2011-05-17, KevinCameron)EditAttach The SystemVerilog Discrete (analog) modeling Committee (SV-DC) is responsible for adding support for user defined types to SV which will include support for types like "wreal".
| I | Attachment | Action | Size | Date | Who | Comment |
|---|---|---|---|---|---|---|
 pdf |
3398-alt.pdf | manage | 109.1 K | 2011-05-17 - 06:59 | KevinCameron | Alternative user-defined types on nets proposal |
Edit | Attach | Print version | History: r1 | Backlinks | Raw View | Raw edit | More topic actions
Topic revision: r1 - 2011-05-17 - 07:01:12 - KevinCameron
VerilogAMS Web
Create New Topic
Index
Search
Changes
Notifications
Statistics
Preferences
Main |
|
Copyright © 2008-2025 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki? Send feedback
Ideas, requests, problems regarding TWiki? Send feedback