DiscreteAnalogModelingInSV < VerilogAMS

VerilogAMS Web>AmsDiscussionDoc>DiscreteAnalogModelingInSV (2011-05-17, KevinCameron) (raw view)EditAttach

The SystemVerilog Discrete (analog) modeling Committee (SV-DC) is responsible for adding support for user defined types to SV which will include support for types like "wreal".

   * [[http://www.eda.org/sv-dc/hm/][SV-DC Reflector]]
   * [[http://www.eda.org/svdb/view.php?id=3398][Mantiss Item]]
   * [[%ATTACHURL%/3398-alt.pdf][ Alternative user-defined types on nets proposal]]

Attachments

I	Attachment	Action	Size	Date	Who	Comment
pdf	3398-alt.pdf	manage	109.1 K	2011-05-17 - 06:59	KevinCameron	Alternative user-defined types on nets proposal

Topic revision: r1 - 2011-05-17 - 07:01:12 - KevinCameron

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