Analog Mixed Signal Glossary

The meaning of terms used in mixed-signal and analog simulation.

Piecewise Linear - PWL

A signal that has discrete values in the first derivative is known as piecewise linear, see Wikipedia - Piecewise Linear Function.

Driver

In simulation languages the "driver" is the interface object between a discrete-time process and a signal (or wire) which is used to assign a value to the signal. The concept is important because there may be multiple drivers (from different processes) for one signal (in which case resolution is required).

Analog-To-Digital Converter Element - A2D

A2D is the shorthand for Analog-To-Digital converter element (see D2A).

Digital-To-Analog Converter Element - D2A

D2A is the shorthand for Digital-To-Analog converter element. D2As and A2Ds are inserted into the simulation to convert Drivers to Contributions and analog levels to discrete events in Receivers.

Contribution

A "contribution" is the continuous time version of a "driver". For a mixed-signal net drivers are converted to contributions by D2As.

Receiver

In Verilog-AMS "receiver" refers to the interface object between a discrete-time process and a signal which relays the signal's value into the process. This is required in AMS because an analog signal level may translate into different logic levels for different processes (say high-vt vs low-vt cells). In purely discrete simulation receivers are essentially pass-through, in mixed-signal simulation the receiver can be an A2D.

Disciplines

Drivers, contributions and receivers belong to disciplines e.g.: electrical, fluid dynamic, magnetic. You cannot connect drivers, contributions or receivers of different disciplines together on the same net.

Net

A net is the object in a simulator that drivers, recevers and contributions are connected to, usually it represents a single physical wire.

Node

A node is the simulation object that is used in calculation of a net's value - see Nodal Analysis

Port

Ports are used in HDL and schematic descriptions to tie nets at one level of hierarchy to nets at another level of hierarchy.

(Simulation) Domain

The domain of simulation determines the kind of simulation algorithms used, Verilog-AMS supports "discrete" and "continous" (i.e. digital and analog).

Resolution

Resolution is the process of determining what value appears on a signal when there are multiple drivers.

Out-Of-Module Reference - OOMR, sometimes XMR

A reference from one module instance to an object in another module instance in instantiated hierarchy. An essential piece of the Verilog(-AMS) language that allows upper levels of a hierarchy to probe/connect lower levels outside of defined port connections. In AMS it can be used for parasitic insertion or cross-coupling.

-- KevinCameron - 20 Apr 2009