(r1) AmsExamplesADCM < VerilogAMS

VerilogAMS Web>AmsExamples>AmsExamplesADCM (revision 1) (raw view)~~EditAttach~~

---+ Analog/Digital Converters and Modulators (ADCM)
| *Type* | *Description* | *Source* |
| [[#DAC][Ideal DAC]] | Ideal digital/analog converter with variable converter size | [[%ATTACHURL%/ideal_dac.va][ideal_dac.va]] |
| [[#ADC][Ideal ADC]] | Ideal analog/digital converter with variable converter size | [[%ATTACHURL%/ideal_adc.va][ideal_adc.va]] |
| [[#FOSD][First Order Sigma-Delta]] | First order sigma-delta converter | [[%ATTACHURL%/firstorder_sigmadelta.va][firstorder_sigmadelta.va]] |
| [[#SaH][Sample and Hold]] | Sample and hold model<br /> Sampler model show the application of the sample and hold model with the clock generator | [[%ATTACHURL%/sample_hold.va][sample_hold.va]]<br />[[%ATTACHURL%/sampler.va][sampler.va]] |
| [[#QAM][QAM]] | Quadrature amplitude modulator | [[%ATTACHURL%/qam16.va][qam16.va]] |
---++ <a name="DAC">Ideal Digital/Analog Converter</a>
| *Module Name* | ideal_dac |
| *Terminals* | in: input vector with digital code : input [0:dac_size-1] voltage<br /> out: analog output terminal : output voltage |
| *Parameter* | dac_size: size of converter = 8 from (1:inf)<br /> vth: threshold voltage for input code<br /> trise: rising time at output = 0<br /> tfall: falling time at output = 0 |
---++ <a name="ADC">Ideal Analog/Digital Converter</a>
| *Module Name* | ideal_adc |
| *Terminals* | in: analog input terminal : input voltage<br /> clk: clock terminal : input voltage<br /> out: output vector for digital code : output [0:adc_size-1] voltage |
| *Parameter* | adc_size: size of converter = 8 from [1:inf)<br /> fullscale: range of the analog input : 1.0<br /> delay: delay time until output starts changing after rising clock : 0<br /> trise: rising time at output = 10n<br /> tfall: falling time at output = 10n<br /> clk_vth: threshold voltage for input code<br /> out_high: output high voltage = 1<br /> out_low: output low voltage = 0 |
---++ <a name="FOSD">First Order Sigma-Delta Converter</a>
| *Module Name* | firstorder_sigmadelta |
| *Terminals* | in : analog input terminal : input voltage<br /> clk : clock terminal : input voltage<br /> out : output terminal : output voltage |
| *Parameter* | quantizer_vth: threshold voltage for internal quantizer = 0<br /> clk_vth: threshold voltage for clock input = 2.5<br /> d2a_gain: gain of the internal digital/analog converter = 5 |
---++ <a name="SAH">Sample and Hold</a>
| *Module Name* | sample_hold |
| *Terminals* | in: input terminal : input voltage<br /> clk: clock terminal : input voltage<br /> out: output terminal : output voltage |
| *Parameter* | slewrate: slew rate at the output : 1ns<br /> clk_vth: threshold voltage for clock input = 2.5 |
---++ <a name="QAM">Quadrature Amplitude Modulator</a>
| *Module Name* | qam16 |
| *Terminals* | in: input terminal : input [0:3] voltage<br /> out: output terminal : output voltage |
| *Parameter* | freq: modulation frequency = 1.0<br /> ampl: output amplitude = 1.0<br /> thresh: input threshold voltage = 2.5<br /> tdelay: delay time = 0<br /> ttransit: transition time = 1/freq |

-- Main.DavidMiller - 2011-03-01

Attachments

I	Attachment	Action	Size	Date	Who	Comment
va	firstorder_sigmadelta.va	manage	1.1 K	2012-09-14 - 15:53	DavidMiller	First order sigma-delta converter
va	ideal_adc.va	manage	1.4 K	2012-09-14 - 15:53	DavidMiller	Ideal analog/digital converter with variable converter size
va	ideal_dac.va	manage	1.0 K	2012-09-14 - 15:54	DavidMiller	Ideal digital/analog converter with variable converter size
va	qam16.va	manage	1.0 K	2012-09-14 - 15:54	DavidMiller	Quadrature amplitude modulator
va	sample_hold.va	manage	1.2 K	2012-09-14 - 15:54	DavidMiller	Sample and hold model
va	sampler.va	manage	1.1 K	2012-09-14 - 15:54	DavidMiller	Sampler model show the application of the sample and hold model with the clock generator

Topic revision: r1 - 2012-09-14 - 15:54:54 - TWikiGuest

VerilogAMS