Date: Thursday 16th June 2011


Ken Bakalar Mentor Grahics
Ian Wilson Berkeley DA
Dave Miller Freescale
Scott Little Freescale
Geoffrey Coram Analog Devices
Dave Cronauer Synopsys
Sri Chandra Freescale

Update on document editing

  • Working with P1800 committee to get the original frame source of 2009 version. Document edits will be done to keep on the P1800 version.
  • For the time being, a word document is being generated which records the changes and updates required in the final merge, until Accellera committee gets access to the source.
  • We need further contribution/volunteers to participate in this effort to make this successful and in a meaningful timeframe. Currently there is not enough contribution on the various chapters apart from Dave Miller and Graham Helwig.

Interconnect proposal from SV-DC committee

  • * Discussion on SV-DC proposal on user defined net types and using generic interconnect objects.
  • The proposal from SV-DC as it stands today seems to be fine from the Verilog-AMS technical committee. Currently this is done in AMS through the overloading of the "wire" concept, which is not probably the right way to go about. The new proposal does not seem to break backward compatibility.
  • Discussions around wreal and its connection mechanism to wire?
  • How does the current usage of discipline work with the user defined net types?
    • The aspect of disciplines is outside the scope of this work from SV-DC and there is no intention to look at that.
    • How will this be handled in SV-AMS integration? The AMS technical committee also feels it is not good idea to overload "electrical discipline" and prefers the usage of "interconnect" keyword that is specified in the proposal
    • There seems to be lack of clarity, based on discussions, on the intent of the discipline used in Verilog-AMS vs net type.
  • The interconnect proposal is purely to specify structural connections to bridge the gap in SV where there was no structural connection available in SV before.
  • The current connectivity syntax in SV is very restrictive - only real to real connection; done on intent.
    • Possibly look at removing the restrictions as we move forward with SV-AMS

Next call

To be scheduled at a later date

-- DavidMiller - 2011-06-14

Topic revision: r1 - 2012-03-13 - 15:52:54 - DavidMiller
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