New VHDL Interface Construct

Heterogeneous Interface Examples

Interface Whiteboard for Brainstorming

Heterogeneous Interface Requirements

Interface Mode Requirements

Interface Bundle Requirements

Something new to play with!

I felt that the Email reflector can become confusing with long threads being generated and the TWiki requirements page structure is perhaps a bit too structured (for hacking about). So I've put theses 'sandbox' pages together with the hope that we can get something closer to real-time discussion of ideas.

The aim of these pages is to provide a series of whiteboard disussion pages for a new VHDL interface construct.

TWiki gives us a pretty good revision control mechanism and so these pages should be treated as a true whiteboard i.e. cut & paste to your hearts delight. If we need something we can always recover it!

I am hoping this can provide a brainstorming facility where we can play around with ideas and concepts, hopefully ending with a good solution.

The following links are to;

• a page of requirements and relevent Emails/documents/web-pages;
  • Interface Requirements and Documents

• my initial arrempts at writing some BNF productions;
  • Interface BNF Syntax

• and lastly, the incredibly complex CPU bus interface example that I posted on the Email reflector.
  • CPU Bus Interface Example

• The formal requirement:
  • Interface Construct and Port Mode Configurations

If someone could try and edit these pages just in case there are any access controls set it would be much appreciated. My sandbox is currently the parent so if there are problems with access, we can move it out to the geneal sandbox pit.

These initial scrawls are very much aimed at RTL use, but do please start adding stuff for verification/test-bench enhancements as well.

-- Brent Hayhoe

These initial scrawls are very much aimed at RTL use, but do please start adding stuff for verification/test-bench enhancements as well.

Reference links:

• Proposals:
  • Records with Directional Subtypes - Peter Flake
  • Add a "Bus" port mode for bidirectional port signals - Brian Drummond
  • Interface Construct and Port Mode Configurations - Brent Hayhoe
  • Interfaces: Packages as an Interface Construct - Jim Lewis
  • Protected Types with Public Signals - Jim Lewis
  • Protected Type: Shared Variables On Entity Interface - Jim Lewis
  • Record Introspection - Chris Higgs
  • Record Introspection & Indexing - Brent Hayhoe
  • Generics on Protected Types - Jim Lewis
  • IR2067 - Logical link interface abstraction - Martin Trautmann, analyzed: Peter Ashenden
  • IR2076 - a member attribute for records - Rickard Norberg
  • IR2089 - Directional Records - Andreas Doering, never analyzed
  • IEEE 200X FT-17 - Composite interface mode - Jim Lewis
  • IEEE 200X FT-14 & FT-15 - Arrays of unconstrained arrays and records with unconstrained arrays - Ryan Hinton

• Documents:
  • SUAVE Language Description - Peter Ashenden
  • Interfaces - Jim Lewis
  • Object Orientation Revisited - Peter Ashenden

• Email threads:
  • vhdl-200x: Requirements for VHDL Interfaces
  • vhdl-200x: Requirements for Interfaces
  • vhdl-200x: Re: Requirements for Interfaces, Part 1
  • vhdl-200x: Re: Requirements for Interfaces, Part 2
  • VHDL Interfaces (was RE: EXTERNAL: Re: vhdl-200x: VHDL enhancements wish list)
  • vhdl-200x: Directional records proposal
  • {Disarmed} Re: vhdl-200x: Directional records proposal
  • vhdl-200x: Records with diectional subtypes
  • vhdl-200x: Interfaces with normal, conjugated and monitor flavours