Interface Bundle Requirements

• Interfaces were originally conceived as using the standard record type to group various signal types together.

• A VHDL-AMS requirement extended this concept to include multiple objects (terminal and quantity objects).

• Bundles encompassing objects may be of use within standard VHDL particularly when connecting to subprogram parameters.

• A bundle requires a new object to carry/transport the connection between interface termini, in a similar manner to signals of record type were used in the original proposals.

• The group construct was suggested as a possible method for encapsulating this new object bundling:
  • The group object first defines a template of the objects to be grouped together.
  • A group then groups together named objects of the class defined by the template.
  • Groups were introduced as a mechanism to apply the same attributes to a number of different objects.
  • Because groups do not specify the types of object classes, they are probably not useful for bndle specification.

• Specify a bundle template:

      bundle
         group CPU_bg is 
            signal DATA       : DATA_st;
            signal ADDR       : ADDR_st;
            signal R_W        : Std_Logic;
            signal SLAVE_SEL  : SLAVE_SEL_at;
            signal SLAVE_DATA : SLAVE_DATA_at;

      end group CPU_bg;

• • Similar to a record type declaration
  • Objects may be of class signal, shared variable, constant or file
  • VHDL-AMS will add the extra classes of quantity and terminal

• An element of a bundle template will have a type and an object class associated with it.

• A bundle template will itself be an object class that can be included within another bundle template. Bundles then become hierarchical.

• A bundle template can be declared in a package.

• A bundle must be able to be declared as an object in order to connect termini of interfaces, cf. signals.

      bundle CPU_b : CPU_bg;
 

• A bundle template can be declared in an architecture or subprogram.

• The bundle template must be able to be used in a new modport construct to specify port/parameter modes individually for its elements.

• If a bundle object contains signals and variables, different parts will update at different delta times.

• Can bundles be assigned and do we need a new assignment operator for a mixed bundle. Neither "<=" nor ":=" would seem to be appropriate.