p1800 System Verilog Special Committee (SV-SC) Home Page

What is the "Special Committee"?

This is a committee formed specifically to define the new "checker" constructs. This is a proposal originally approved by the SystemVerilogAssertionCommittee, that turned out to be more controversial than originally expected. Thus this new committee was formed to come up with a full definition that all stakeholders can accept. While focused on checkers, the discussion also encompassed related issues such as 'let' statements, free variables, and general assertions in procedural code.

Logistics

Current Status (updated 2008-11-11)

  • Summary: All approved proposals are implemented in Draft 7 and reviewed by owners, except for a couple of new proposals that must be driven as ballot issues.

Working Documents

Other Useful Links

About This Page

This is a "Wiki", which means a user-editable web page. If you are an active member of the SV-SC committee, feel free to make updates, corrections, and additions! For questions about this page, contact Erik Seligman.

-- ErikSeligman - 11 Apr 2008

Topic revision: r34 - 2008-11-11 - 15:45:44 - ErikSeligman
 
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