SystemVerilogSpecialCommittee < P1800

P1800 Web>SystemVerilogSpecialCommittee (2008-11-11, ErikSeligman) (raw view)EditAttach
---+ p1800 System Verilog Special Committee (SV-SC) Home Page

---++  What is the "Special Committee"?
This is a committee formed specifically to define the new "checker" constructs.  This is a proposal originally approved by the SystemVerilogAssertionCommittee, that turned out to be more controversial than originally expected.  Thus this new committee was formed to come up with a full definition that all stakeholders can accept.  While focused on checkers, the discussion also encompassed related issues such as 'let' statements, free variables, and general assertions in procedural code.

---++ Logistics
   * Chair:  [[mailto:Erik.Seligman@intel.com][Erik Seligman]], Intel
   * Co-Chair:  [[mailto:Thomas.Thatcher@sun.com][Tom Thatcher]], Sun
   * To subscribe to [[mailto:sv-sc@eda.org][the mailing list]], send an email to majordomo@eda.org with "subscribe sv-sc your_email_address_here" in the body.
      * [[http://www.eda-stds.org/sv-sc/hm/][SV-SC Email Archive]]
   * The 2008 work for this committee is complete, so weekly meetings are no longer being held.  We may schedule a meeting to discuss reviews of Draft 7 if necessary.
      * [[SvScMeetingMinutes][Meeting Minutes Page]]
   * [[http://www.verilog.org/mantis/main_page.php][Mantis database]]


---++ Current Status (updated 2008-11-11)
   * Summary:  All approved proposals are implemented in Draft 7 and reviewed by owners, except for a couple of new proposals that must be driven as ballot issues.

   * Ballot issue proposals, which arrived too late for official inclusion in drafts:
      * [[http://www.verilog.org/mantis/view.php?id=2513][2513:  BNF fixes related to 1900]]
      * [[http://www.verilog.org/mantis/view.php?id=2516][2516:  More Self-Consistency Fixes related to 2398]]

   * New proposal passed based on Draft 7 review, implemented in 7a.
      * [[http://www.verilog.org/mantis/view.php?id=2483][2483:  Self-Consistency Fixes related to 2398]]

   * Passed by SV-SC and champion edits complete, implementation under review by reviewers below:
      * [[http://www.verilog.org/mantis/view.php?id=1728][1728:  Let Statements]]:  Dmitry, Manisha
      * [[http://www.verilog.org/mantis/view.php?id=2414][2414:  Let VPI]]: Abi, Ed
      * [[http://www.verilog.org/mantis/view.php?id=2088][2088:  Covergroups in Checkers]]: Tom, Francoise
      * [[http://www.verilog.org/mantis/view.php?id=2415][2415:  ended/triggered fixes]]: Dmitry, Jin
      * [[http://www.verilog.org/mantis/view.php?id=2396][2396:  @edge clk]]: Jin, Lisa
      * [[http://www.verilog.org/mantis/view.php?id=2434][2434:  1549 update:  self-determined types]]: Gord, Mark
      * [[http://www.verilog.org/mantis/view.php?id=2398][2398:  Concurrent Asserts in Procedural Code:  New semantics]]:  Erik, Gord
      * [[http://www.verilog.org/mantis/view.php?id=1900][1900:  Checkers]]:  Part 1: Tom, Dmitry;  Part 2a, 17.1-17.4: Erik, Mirek; Part 2b: 17.5-end: Mike, Lisa

   * Votes passed to close as duplicates
      * [[http://www.verilog.org/mantis/view.php?id=2370][2370: $past in Procedural Code]]: vote to close as duplicate of 1698
      * [[http://www.verilog.org/mantis/view.php?id=1995][1995:  Concurrent Asserts in Procedural Loops]]  vote to close as superseded by 2398
      * [[http://www.verilog.org/mantis/view.php?id=2089][2089:  Final in Checkers]]: vote to close as duplicate of 1900
      * [[http://www.verilog.org/mantis/view.php?id=2241][2411:  Allow tiriggered in sequences]]:  Vote to close as duplicate of 2415
      * [[http://www.verilog.org/mantis/view.php?id=2110][2110:  Checkers in procedural loops]]:  Vote to close as superseded by 1900

   * Dropped for this PAR
      * [[http://www.verilog.org/mantis/view.php?id=2413][2413:  Inferred functions in let]]  
      * [[http://www.verilog.org/mantis/view.php?id=2412][2412:  Clock inference in sequences]] 
      * [[http://www.verilog.org/mantis/view.php?id=2182][2182:  VPI Diagrams for Checkers]]  (Chuck Berking) 



---++ Working Documents
   * [[AssertionMotivations][Tom's summary of our goals regarding assertions]]
   * [[SVACheckerMotivation][Dmitry's summary of motivations for checkers in SVA]]
      * [[F2FCheckerSummary][Erik's summary of checker decisions made at May 2008 F2F]]
   * [[http://www.eda-stds.org/sv-sc/hm/att-0049/EmbeddedConcurrentAssertions__080422dk.pdf][Dmitry's summary on concurrent assertions in procedural code]]
   * [[ConcurrentAssertNewProposal][Gord's summary of the proposed new semantics for concurrent asserts in procedural code]]
      * [[TomProceduralAssertExamples][Some motivating examples from Tom]]
      * [[http://www.eda-stds.org/sv-sc/hm/att-0154/assertions_deferred-f2f.ppt][Gord's presentation on the new proposal]]
   * Typing and property/checker/let arguments
      * [[GordLetTyping][Gord's summary of typing concerns for Let]]
      * [[http://www.eda-stds.org/sv-sc/hm/att-0154/assertions-f2f.ppt][Gord's presentation on type argument issues]]
   * [[http://www.eda-stds.org/sv-sc/hm/att-0165/Let.ppt][Dmitry's presentation on Let]]
   * [[CurrentProposalFixesNeeded][Fixes needed to pre-Draft6 proposals, as identified by committee reviews]]




---++ Other Useful Links
   * [[http://sv-ac.pbwiki.com][SV-AC committee web page]]
   * [[http://www.eda-stds.org/sv-ac/hm/][SV-AC (assertion committee) email archive]]
   * [[http://standards.ieee.org/board/pat/pat-slideset.ppt][Patent Policy]]

---+++ About This Page
This is a "Wiki", which means a user-editable web page.  If you are an active member of the SV-SC committee, feel free to make updates, corrections, and additions!  For questions about this page, contact [[mailto:Erik.Seligman@intel.com][Erik Seligman]].

-- Main.ErikSeligman - 11 Apr 2008
Topic revision: r34 - 2008-11-11 - 15:45:44 - ErikSeligman
P1800