SvScMeetingMinutes20080428 < P1800

P1800 Web>SystemVerilogSpecialCommittee>SvScMeetingMinutes>SvScMeetingMinutes20080428 (2008-05-05, ErikSeligman) (raw view)EditAttach
<verbatim>
=================Attendance=============================

   220 Day
   817
   000 Month
   444
   000 Year
   888

-[--a]   Arturo Salz          - Synopsys
v[aa-]   Abigail Morehouse    - Mentor
-[--a]   Bassam Tabbara       - Synopsys
-[--a]   Brad Pierce          - Synopsys
v[aaa]   Cliff Cummings       - Sunburst Design
v[aaa]   Dave Rich            - Mentor Graphics
v[-aa]   Dmitry Korchemny     - Intel
v[aa-]   Don Mills            -
v[aaa]   Eduard Cerny         - Synopsys
t[aaa]   Erik Seligman        - Intel (chair)
v[aaa]   Francoise Martinolle - Cadence
v[aaa]   Gordon Vreugdenhil   - Mentor Graphics
v[aa-]   Jin Yang             - Intel
v[aaa]   John Havlicek        - Freescale
-[--a]   Jonathan Bromley     - Doulas
v[a-a]   Karen Pieper         - Accellera
v[aaa]   Lisa Piper           - Cadence
v[aaa]   Manisha Kulshrestha  - Mentor Graphics
v[aaa]   Mark Hartoog         - Synopsys
v[aaa]   Mehdi Mohtashemi     - Synopsys
v[aaa]   Mirek Forczek        - Aldec
v[aaa]   Neil Korpusik        - Sun Microsystems
-[-a-]   Ray Ryan             - Mentor
v[-aa]   Shalom Bresticker    - Intel
v[aaa]   Steven Sharp         - Cadence
v[aaa]   Stu Sutherland       - Sutherland HDL
v[-aa]   Surrendra Dudani     - Synopsys
v[aaa]   Tom Thatcher         - Sun Microsystems (co-chair)
|
|---- Voting eligibility for next meeting


====================Agenda==============================
Agenda:

      1. Review the patent policy
      2. Approve the minutes from the April 21, 2008 meeting, available at
     http://www.eda.org/twiki/bin/view.cgi/P1800/SvScMeetingMinutes20080421
      3. Review of action items (no major items not covered in rest of
     agenda, so will skip unless someone has specific concern)
      4. Logistics topics
     + Meeting time change: swap with SV-AC, so future SC meetings on
       Tues. Need to approve by voice vote.
     + Face-to-face: Confirm for Wed 5/14- Thurs 5/15 in Bay area. Find
       volunteer hosts, or assign action item to get venues.
      5. Technical topics
     + Concurrent assertions in procedural code: review Dmitry's points
       (Erik to lead discussion since Dmitry on vacation), try to converge
       to concrete proposal to be written by following week.
     + Checkers as variant modules: Review Gord's email concerns, try to
       converge on documented set of issues preventing/supporting inlining
       semantics.
     + Let statements: If time remains, review concerns here and
       attempt to come up with concrete issue list.


====================Notes==============================

1.  Patent policy.
2.  Minutes
     Gord:  Move to accept minutes
     Cliff: Second

3.  Meeting time:  Propose to swap sc-ac and sv-sc meeting.
     SV-AC would meet on Mondays,
     SV-SC would meet on Tuesdays
     Gord:  Move to swap sv-ac and sv-sc meetings
     Neil:  second
     No abstentions, no no votes.

4.  Face to face
     May 14/15 in Bay area.
     Dave Rich:  Should be able to host one day (May 14) at Mentor.
     Neil:  Will check for a room at Sun
     Gord:  No need to vot on this.

5.  Scheduling
     Erik sent out a tenative schedule for sv-sc work.
     Tom:  Should split checker topic into two topics:
         checkers and checker variables.
     Erik:  Schedule calls for completion by june.  (allows for slippage)


     Tom: Move to accept tenative schedule
     Karen:  second
     Gord: abstain
     Steven: abstain
     Motion passes with two abstentions.

6.  Assertions in procedural code
     Dmitry has sent a doc

     Issues:
     - Inference of enabling condition is problematic:  Assertion enabled
       using sampled value of inferred enable, while procedural logic
       is executed using current values.
     - Assertions use sampled values, which the requires special rules for
       loop control variables, blocking assignments in sequential
(always_ff)
       procedures, etc.

     Possible solutions
         - Make it illegal to put an assertion in a spot where ambiguity exists
       i.e. right after a blocking assignment.
     - Make it illegal to assign a signal which appears in an assertion
       using a blocking assignment.

     - Use shadow variable instead of sampled value.
     - Mirek's proposal:  Use the control flow of a procedure as the
       enabling condition and clocking event for an assertion which appears
       in a procedure.

     Dave Rich:  Take a step back:  a complete solution would allow for
         concurent assertions in tasks & functions.
     Steven:    Synthesis tools know how to handle blocking assignments in
         sequential procedures properly.  Should simulator do the same?
     Gord:   Need a solution which is more than coding guidelines.
     Dave:   Don't define the solution in terms of restrictions.
         i.e.  assertions not allowed in function calls
         Would need to come up w/ necessary synthesis semantics.

     Steven:  Doesn't like the fact that assertions don't execute in the flow
         of the procedure.

     Mirek: Proposal for Control flow used to trigger assertion
     Steven:  This proposal would be acceptable
         But still have problem of inferring clock for temporal

     Fransois:  We would know how to trigger assertion, but don't know when to
         turn the assertion off
     Dave:  Expect sequences behave similarly
     Dave:  Intent was for for concurrent assertions to have same behavior
         regardless of placement.
     Mark:  Problem:  always block can execute multiple times.
         This proposal would introduce glitch problems
     Steven:  Would need to disable second iteration of execution
     Gord:  This will now work for loops

     Steven:  Another case:  What about a variable assigned from loop index.
     Gord:  Need capability to explicity describe which variables use sampled
         value, which use current value.
     John:   Agreed (he had suggested this last meeting)
     Mark:  Automatic variables could automatically use current value.
     Erik:  This allows for loop variables for assertions in loops.
     Gord:  Only if the loop index is a true automatic.  Old style code would
         need this new explicit method to use current value.
     Tom:  This would also fix cases for assertions outside procedural code.
     Mark:  We could be moving toward a glitch problem for enabling condition

     Steven:  Would you ever need to use both sampled and current value?

     AI:  Gord will write up an informal proposal for assertions in procedural
         code.  Will contain some proposed syntax, and some summary of how
         it might work.


2.  Checkers

     Erik:  Do we treat checkers as special kinds of modules?
         Are untyped arguments the main reason why we can't treat them as
         modules?
     Gord:  Checker names are in module namespace.  They would be global.
         Is that the intent?
     Steven:  This is expected.
     Steven:  Modules within modules have local names.
     Mark: they behave as properties in name space
     Steven:  Could define  modules in package
     Gord:  Not sure if there is an issue for untyped
         Could inlining be just ane expression of type parameterization? 
  Not
         sure.  Also objected to use of "parse" in the 1549 proposal.
     Steven:  Seems that sequences/properties are like macros
     John.  1549 These were written to clarify what could be passed as an
         argument We may have got some things worng
     Steven must be completed
     Gord:  Do you have to look inside property/sequence body to reason about it
         If so, then inlining semantic is required.  (Not ideal)
         Is the prototype expression enough to reason about the instance?
     Mark:  I don't think reparsing is necessary.
     Gord:  Inferred stuff may cause more dependencies.

     Manisha:  One concern:  Rules for passing acutals not well defined.
     Because of substitueion semantics, need to clarify rules.

     Mark:  Sequences/Properties Not being passed by value, or reference,
         really.  Need clarification.  It's a fundamentally different
         composition.  NOt so upset that it behaves differently.
     John:  1549 does contain some clarification of type casting rules.

     John & Gord will work together offline to understand the passing of
         arguments to properties & sequences.


     (Back to assertions in procedural code topic)
     Steven:  Idea of triggering, rather than clocking:  Could get us closer
         to putting concurrent assertions within tasks or functions.

     Gord:  Passing clock argument by reference could solve some problems.
     John:  This is allowed currently.  It is just a certain style of coding
     Ed:   But can't pass expressions by reference


Meeting adjourned

NOTE   Next meeting will be Tuesday, May 6,  9:00-11:00 PDT

</verbatim>



-- Main.ErikSeligman - 29 Apr 2008
Topic revision: r2 - 2008-05-05 - 17:34:50 - ErikSeligman
P1800