P1076.1-201X Revision
Scope of the Standard
This standard defines the IEEE 1076.1™ language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. Informally called VHDL-AMS, (VHSIC Hardware Description Language for Analog and Mixed-Signal, where VHSIC stands for Very High Speed Integrated Circuits), the language is built on the IEEE 1076™ (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.
Purpose of the Standard
To support the design and verification of complex electronic systems containing a mixture of analog and digital devices, the IEEE 1076.1™ language provides, as an extension of the IEEE VHDL 1076 language, a comprehensive set of capabilities for the description and simulation of mixed-signal and mixed-technology systems.
The revision adds selected new features to the language definition of the 1076.1-2007 standard, and updates the 1076.1-2007 standard to reflect changes in the VHDL 1076-2008 specification.
New or Enhanced Functionality in IEEE Std 1076.1-201x
This revision of IEEE Std 1076.1-2007 includes the following:
As a result of this work, the draft standard now includes, in addition to the functionality present in 1076.1-2007, the following major functionality that was either inherited from 1076-2008 or 1076.1.1-2011, or gained by extending the 1076.1-2007 functionality along the lines drawn by 1076-2008:
- VHPI; this support is restricted, as in 1076-2008, to the language constructs supported by IEEE Std 1076-2002
- Standard tool directives, including protect tool directives that support IP protection for VHDL-AMS source files
- Enhanced generics. In addition to the corresponding definitions in VHDL-1008, this revision adds generic natures/subnatures
- Extensions to the type system, including partially constrained array types and record types. Similar functionality has been defined for array natures and record natures.
- External names, extended to support external terminal names and external quantity names
The changes in document organization in 1076-2008 required various modifications to the document structure of this revision. Specifically, all clauses were renumbered in 1076-2008 to conform to IEEE style requirements; the new numbering has been retained. In addition, the formerly separate clause defining
simultaneous statements has become part of the clause defining Architecture statements (in 1076-2008: Concurrent statements). At the same time, to increase clarity, 1076-2008 concurrent statements whose purpose is to define the design hierarchy have been grouped as
structural statements, with
concurrent statements now referring to those statements that do not define design hierarchy. This is a change in classification only, no change was made to the definition of the statements itself.
This revision also includes selected new VHDL-AMS-specific functionality:
- A new signal ASP_DONE that toggles its value each time an analog solution point (ASP) has been determined. This signal allows a model to perform actions at an ASP, for example writing the value of selected quantities to a file.
- Support for limited modeling in the frequency domain. The use model supports, for example, defining the behavior of a design unit in the frequency domain by reading a complex transfer function from a file.
Several projects that were initially planned to be part of this revision did not get included in the end:
Finally, this revision fixes several issues present in
IEEE Std 1076.1-2007 or
IEEE Std 1076.1-2011.
Language Change Specifications
The LCSs for this language revision are available in a
Member-only area.
Standard Document
Alain Vachoux is the Editor for this revision of the language.
All files related to the development of the standard document are in a
Member-only area.
Machine-Readable Files
Machine-readable files include source code for the standard packages and VHPI-related files, including UML diagrams.
The machine-readable files are available
here.
Activities Related to Approval and Publication of the Revision
Private area related to ballot
- A vote by the Working Group Members to approve the draft document for release to an IEEE ballot was initiated on February 12, 2017, with a 1-month duration to give people enough time to review the draft document. The draft document and the packages were made available to the WG members on a secure site. The vote was unanimous to approve the document.
- Mandatory Editorial Coordination was initiated on March 18, 2017 and acknowledged by IEEE-SA on March 19. It ended on April 12, with an email indicating that no issue had been found.
- The formation of the ballot pool was initiated on March 18, 2017 and started one day later. 14 people signed up:
Classification |
Count |
Percentage |
---|
Producers |
4 |
28% |
Users |
4 |
28% |
General Interest |
4 |
28% |
Government |
1 |
7% |
Service Provider |
1 |
7% |
Total |
14 |
100% |
The ballot pool is balanced as each class size is less than 1/3 of the pool and the members have 13 different affiliations.
- The ballot was initiated on May 2, 2017, and balloters were notified on May 3. At the close on June 2, 1017, at 11:59 pm EDT, the results were as follows:
|
Count |
Percentage |
Requirements |
---|
Size of ballot pool |
14 |
100% |
> 10 |
Votes returned |
14 |
100% |
> 75% |
Abstentions (lack of expertise) |
2 |
14% |
< 30% |
Non-abstention votes |
12 |
86% |
|
Approve |
12 |
100% |
> 75% |
Disapprove |
0 |
0% |
|
Since the requirements are met, the ballot passes.
- No comments were returned by the balloters.
- Public review ended on July 2, 2017. No comments were received.
- The draft material was submitted to RevCom on July 26, 2017.
- RevCom recommended approval of P1076.1 version D1.2 on September 6, 2017.
- The IEEE-SA Standards Board approved the revision as IEEE Std 1076.1-2017 on September 28, 2017.
- IEEE Std 1076.1™-2017 was published by IEEE-SA on January 24, 2018.
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ErnstChristen - 2013-05-06