IEEE 1076.1 Project Area

This page includes a number of links to projects currently under works in the 1076.1 Working Group. The access to the project pages are restricted to registered working group roster members (login required).

Three categories of projects are defined:

  • Upgrade projects to align the 1076.1 standard to the 1076 standard.
  • Maintenance projects for the 1076.1 standard (e.g., errata, clarifications of language definitions, integration of external standard packages).
  • New feature projects to add new functionality in the 1076.1 standard.

We also consider assigning a project complexity level of 1 to 5 (with 5 being the most complex) to allow comparison of effort.

The projects shall be conducted along the following steps:

  1. Define priorities (WG vote or consultation based on project summary and meeting presentations).
  2. Select project champions and related teams.
  3. Document requirements, review and approve by WG.
  4. Develop language change specifications (LCS) or new packages.
  5. Review and approve LCS or new packages by WG.
  6. Update LRM, proceed to IEEE ballot.

Upgrade Projects

Alignment to IEEE Std 1076-2008

Member-only area

The base language for IEEE Std 1076.1, defined by IEEE Std 1076, has introduced significant enhancements in its revision approved in 2008. Incorporating these changes will be an integral and mandatory part of a revision of IEEE 1076.1.

This is not the place to describe all changes that must be accommodated, but an overview of the major enhancements that may affect the 1076.1 language definitions is useful. For more information see this slides or Peter J. Ashenden, Jim Lewis: VHDL 2008 — Just the New Stuff, Morgan Kaufman Publishers, 2008.

IP Protection

The VHDL-AMS user base had already requested supporting a standard form of IP protection for the 2007 revision of the language, but these requests were denied then for two reasons. First, IP protection was planned to be and was subsequently introduced in the base VHDL language in its 2008 revision, but was still undergoing changes at the time when the 1076.1 language revision went to ballot. Second, IP protection was a new feature that did not fit the maintenance character of the 2007 revision of IEEE Std 1076.1.

Supporting IP protection in the next revision of IEEE Std 1076.1 will be a major enhancement to the language. Its complexity level is 1 as the corresponding definitions are almost completely transparent.

VHPI-AMS [Champion: David Smith]

The VHDL Procedural Interface is a application programming interface to VHDL tools. VHPI allows an external application to access information about a VHDL model during analysis, elaboration and execution. This enables the creation of tools such as debuggers or profilers for VHDL models, and it also makes it possible to support foreign models, which are models written in part (foreign subprograms) or in their entirety using a standard programming language like C.

VHPI is based on an abstract data model of a VHDL model. To extend VHPI to support VHDL-AMS, at least the following tasks will be necessary:

  • Augment the abstract model to include the concepts that are specific to VHDL-AMS
  • Extend the VHPI API definitions to provide access to VHDL-AMS-specific objects
  • Add support for VHDL-AMS-specific statements to the VHPI API definitions
  • Add support for the extended 1076.1 simulation cycle to the VHPI API definitions

An overview if similar capabilities in VPI-AMS for Verilog-AMS were discussed at the Working Group meeting of January 12, 2010.

The complexity level of this project is 5.


IEEE Std 1076-2008 allows PSL code to be embedded in a VHDL model. PSL is the Property Specification Language is defined by IEEE Std 1850. It supports the specification of temporal properties of a digital model that can be verified using specialized tools. Colloquially, these specifications are often referred to as assertions.

Extending PSL to support analog and mixed-signal models is outside the scope of the revision of IEEE Std 1076.1.

Other Changes [Champion: Ernst Christen]

IEEE Std 1076-2008 introduced many other enhancements, many of which will be transparent to the VHDL-AMS extensions, in particular those that are specific to digital models. Others will require enhancements to their definition to support VHDL-AMS specific concepts.

The complexity level to accommodate these changes and extend them to support VHDL-AMS is estimated to be 3.

Maintenance Projects

Integration of Packages Defined by IEEE Std 1076.1.1 [Champion: David Smith]

Member-only area

IEEE Std 1076.1.1 is a companion to IEEE Std 1076.1 that provides a collection of standard definitions to support the creation of models in multiple energy domains: electrical, translational, rotational, thermal, and others. Just as IEEE 1076-2008 integrated the previously separate standards defining the packages std_logic_1164, math_real, math_complex, numeric_bit, numeric_std, the plan is to make the 8 packages defined by IEEE Std 1076.1.1 an integral part of IEEE Std 1076.1. The companion standard can then be discontinued.

The complexity level of this integration is 1.


Member-only area

Several minor LRM issues, collected as issue requests. The complexity level of this project is 1.

New Feature Projects

There are several candidates of new features that could become part of a revised 1076.1 standard, provided there are enough resources to work on the corresponding definitions in a timely manner. The candidates fall in one of two categories:

  • Language extensions, which require either changes to the existing language definition or new definitions at the language level.
  • New standard packages.

Mixed Netlists [Champion: Ernst Christen]

Member-only area

The purpose of this project is to define semantics for a connection of a port of one object class to an actual of another, for example a signal port to a terminal. Such connections arise naturally if a user creates a model by instantiating library models in a schematic capture system and connecting their ports. The project dates back to the original definition of IEEE Std 1076.1, when it was postponed due to its complexity. An overview of this project was presented to the Working Group at its meeting on August 18, 2009, were the following requirements were proposed:

  • Support top-down design, by supporting the hierarchical decomposition of a model that includes interfaces between signals, terminals, and quantities.
  • Support unidirectional interfaces (e.g. signal -> terminal, terminal -> signal)
  • Support bidirectional interfaces (e.g. for a bus driver/receiver)
  • Support modeling of such effects as input/output impedance, timing, current drive capability.
  • DO12: The model of the interface between analog and digital descriptions should be customizable by the user. We extend this to also include the interface between terminals and quantities.
  • DO32: Default conversions between analog and digital connection points should be provided. We extend this to also include the interface between terminals and quantities.
  • Support "analog" and "digital" implementations of a design unit that can be selected by configurations.
  • Preserve strong typing inherent in VHDL

A white paper providing some more detail is also available.

The complexity level to define language extensions supporting mixed netlists is 5.

Frequency-Domain Modeling [Champion: Ernst Christen]

Member-only area

IEEE Std 1076.1 supports the description of model behavior in the time domain. Frequency domain simulations are supported in the language definition by three concepts: source quantities, the small-signal model, and the calculation of the quantity values at a given frequency. There are situations where it is desirable to be able to define model behavior in the frequency domain directly, for example when the transfer function of a model is given by measured data.

This project aims at extending the language definition to support such models. An overview how this could be approached was presented and discussed at the Working Group meeting on September 22, 2009. The presentation is based on the paper Proposal to Extend Frequency Domain Analysis in VHDL-AMS by Joachim Haase, Ewald Hessel, Heinz-Theo Mammen presented at FDL'09. It is understood that a likely restriction of such an extension would be that it only supports a frequency domain simulation, i.e. that no time domain model would be derived from the frequency domain description.

The complexity level to define language extensions that support this restricted capability of modeling in the frequency domain is estimated at 2 to 3.

Support for Partial Differential Equations [Champion: Vipin Ahuja]

Member-only area

This project is re-activated.

IEEE Std 1076.1 supports the definition of continuous behavior using differential algebraic equations, which are ordinary differential equations and algebraic equations. There are situations where this is not sufficient to describe the behavior of a device adequately:

  • When creating models of micro-electromechanical systems (MEMS), the geometry of the device affects its behavior such that partial differential equations (PDEs) are required for a useful description.
  • The description of the DC small-signal behavior of a device, popularized by the SPICE family of simulators and used in the context of models of semiconductordevices, requires the availability of a partial derivative.

This project aims at extending the language definition to support partial derivatives and PDEs in a restricted context. Specifically, it is not the goal of this project to extend the language definition to support descriptions useful as input for a device simulator. An approach dealing with MEMS only, based on the method of lines to convert a PDE to a set of difference equations, was first presented at the Forum on Design and Specification Languages in 2007. An updated version was presented and discussed at the Working Group Meeting on October 20, 2009.

The complexity level to define language extensions to support partial derivatives and PDEs is estimated at 3.

Table-driven Modeling [Champion Joachim Haase]

Member-only area

The purpose of this project is to provide a capability to describe the time domain behavior of a device by a (possibly multi-dimensional) table. The need for such a capability may arise if model data has been determined by measurement, but also if the evaluation of the actual model equations is very costly and doing this evaluation once before simulation to create a table proves to be sufficient. Table-driven modeling is supported by Verilog-A(MS), and the goal is to provide a similar capability for VHDL-AMS. An overview of this project was presented and discussed at the Working Group meeting on October 20, 2009, and a collection of requirements is also available.

A preliminary analysis of this project indicates that it should be possible to support the requirements by the implementation of a package. Therefore, it is possible today for users to write such a package. The incentive to make this part of the revised standard is to enable model exchange between users using tools from different vendors. The complexity level to define this package is estimated at 2 to 3.

Vector/Matrix Operations [Champion: Zhichao Deng]

Member-only area

The purpose of this project is the definition of vector/matrix operations to support the description of uniform behavior. For example, the behavior of an N-port linear transformer (N pairs of terminal ports) is compactly described by V = L*dI/dt, where V and I are vectors of voltages and currents and L is a constant matrix with appropriate dimension. Other applications of such operations arise in the context of buses. An overview of this project was presented and discussed at the Working group meeting on October 20, 2009.

A preliminary analysis of this project indicates that it is possible to implement such operations by defining a collection of functions and overloaded operators in a package. The incentive to make this part of the revised standard is to enable model exchange between users using tools from different vendors. The complexity level to define this package is estimated at 2.

Unified Use of SPICE Models in Different Tools [Champion:]

Member-only area

This project is on hold.

Most simulators supporting VHDL-AMS also provide SPICE models (or SPICE-equivalent models) either as built-in primitives or in some other form. Each simulator uses a different methodology to access these models from a VHDL-AMS description. The suggestion is to define a uniform use of such models in different tools to improve model exchange.

Building on this suggestion, the goal of this project is to define a standard method to access in a VHDL-AMS description models that are simulator primitives, with special emphasis on SPICE-equivalent models. A difficulty with such models is that equivalent parameters and sometimes even models may have different names in different simulators. In addition to supporting model access, the concept implemented in SPICE by a .MODEL card should be supported. Some dialects of SPICE also support global nodes. An overview of the project was presented and discussed at the Working Group meeting on September 22, 2009.

A likely approach to provide such access is by means of the definition of a standard package containing component declarations for the SPICE components. It is then left to the vendors to provide the implementation for these models. Issues arise to support the .MODEL card concept and global nodes. The complexity level for this project is estimated at 3.

Dimensional Analysis [Champion: David Smith]

Thre are number of different issues that are related to dimensions and units.

  1. A physical quantity in VHDL-AMS includes the units for those quantities. The units serve little purpose now beyond being used for display purposes of the results.
  2. When to physical quantities of the same type (distance, velocity, temperature) are connected either through quantities or terminals the units (and subtype) currently are not really used in the language for much. A quantity is a special kind of real. Distance is a subtype of real. Any two real quantities can be connected with no error but with no meaning either.
  3. If two physical quantities are representing the physical characteristic there is no check to see if the units are the same. Matter of fact the units are not clearly defined to have semantic meaning and are defined in the 1076.1.1 standard as attributes.
  4. Generics and other “constants” have no units associated with them so there is no possibility of any form of dimensional analysis on expressions to see if there is an error in the expression due to terms.
  5. Numeric literals have no information associated with them indicating what kind data the literal represents.

This project will address all of these issues and provide a way for two quantities that represent the same physical characteristic to have conversion expressions associated with how these values relate (for example 2.54 cm per inch could be used to indicate how to convert inches to cm). The underlying definition of units needs to be SI (as 1076.1.1 provides) but “compatible” units and transformations would provide for models written in different systems to work together.

The result of this will be to support enforcing restrictions on connections based on quantity type, supporting connecting quantities of the same dimension but different units, and support tools performing full dimensional analysis on all expressions in models.

This project aims at investigating this support in the context of VHDL-AMS, including feasibility and scope. The complexity level of this project is estimated at 5.

Miscellaneous Minor Functionality Improvements [Champion: Ernst Christen

  • 'LTF, 'ZTF with poles and zeros. The fact that package ieee.math_complex will be part of the revised standard will greatly facilitate this extension
  • Ability to do something once an ASP has been determined (e.g. write values to a file). Alternatives:
    • A new signal that has an event after an ASP has been determined
    • Postponed simultaneous procedural statement
      • Is executed when an ASP has been determined
        • Purpose is to report simulation results
      • Definition
        • Same declarative items as simultaneous procedural statements
        • Same statements as simultaneous procedural statements, except:
          No variable assignment statement whose target is a quantity
        • See also here for possible additional functionality.
  • Q'integ for periodic functions
    • Like idtmod() in Verilog-AMS
  • Q'Follow(delta[,timeout])
    • A signal whose value follows that of quantity Q with specified accuracy
      • Event when abs(Q-Q'Follow) > delta and NOW-Q'Follow'Last_event > timeout
    • Purpose is real number modeling
    • Corresponds to absdelta() in Verilog-AMS

Topic attachments
I Attachment Action Size Date Who Comment
PDFpdf netlist5.pdf manage 128.2 K 2016-01-21 - 23:58 ErnstChristen White paper on Mixed Netlists
PDFpdf requirements_tlu_modeling_in_vhdl-ams_2006-03.pdf manage 100.9 K 2016-01-21 - 23:59 ErnstChristen TLU modeling requirements
Topic revision: r19 - 2016-09-22 - 23:50:14 - ErnstChristen
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