(r7) SyntaxRegularlization < P1076

P1076 Web>Vhdl2019CollectedRequirements>SyntaxRegularlization (revision 7) (raw view)~~EditAttach~~
---+ Syntax Regularization

%TOC%

---++ Proposal Information
   * Who Updates: Main.JimLewis, ...
   * Date Proposed: 2013-10-20
   * Date Last Updated: 2013-10-20
   * Priority:
   * Complexity:
   * Focus: General Language


---+++ Language Change Specification link

[[TopLCS2016_055][LCS-2016-055]]

---++ Requirement Summary

Current focus on differences between Entity and Component Declarations

[[https://bugzilla.mentor.com/show_bug.cgi?id=258][See Bugzilla 258]]
---++ Rationale

---++ Related Issues: None = General
---++ Competing Issues: None at this time

---++ Current Syntax:

Component Syntax:

<verbatim>
component identifier [ is ]
  [ local_generic_clause ]
  [ local_port_clause ]
end component [ component_simple_name ] ;</verbatim>

Entity Syntax:

<verbatim>
entity identifier is
  entity_header
  entity_declarative_part
[ begin
  entity_statement_part ]
end [ entity ] [ entity_simple_name ] ;</verbatim>

---++ Proposed syntax change for Component Declarations

For components make the final "component" optional.

<verbatim>
component identifier [ is ]
  [ local_generic_clause ]
  [ local_port_clause ]
end [component] [ component_simple_name ] ;</verbatim>

---++ Proposed syntax change for Entity Declarations

For entity declarations make the "is" optional. Not as important. What I am looking for is to simplify copying an entity declaration to create a component declaration.

<verbatim>
entity identifier [is]
  entity_header
  entity_declarative_part
[ begin
  entity_statement_part ]
end [ entity ] [ entity_simple_name ] ;</verbatim>

---++ Generalisation of the proposal

<div id="_mcePaste">To make this 'end' rule consistent throughout the specification the proposed syntax should also be applied to the following syntax rules:</div>

process_statement
<div id="_mcePaste">protected_type_body</div> <div id="_mcePaste">protected_type_declaration</div> <div id="_mcePaste">record_type_definition</div> <div id="_mcePaste">simple_configuration_specification</div> <div id="_mcePaste">generate_statement_body</div> <div id="_mcePaste">block_configuration</div> <div id="_mcePaste">block_statement</div> <div id="_mcePaste">case_generate_statement</div> <div id="_mcePaste">case_statement</div> <div id="_mcePaste">component_configuration</div> <div id="_mcePaste">component_declaration</div> <div id="_mcePaste">compound_configuration_specification</div> <div id="_mcePaste">for_generate_statement</div> <div id="_mcePaste">if_generate_statement</div> <div id="_mcePaste">if_statement</div> <div id="_mcePaste">loop_statement</div> <div id="_mcePaste">physical_type_definition</div>

---++ Possible Issues

For rule 'simple_configuration_specification' using the 'end'-keyword is optional. This might make it impossible for the compiler to determine which rule the 'end' belongs to.

---++ Arguments FOR

---++ Arguments AGAINST

---++ General Comments

Syntax regularization is "busy" work and may not be worthy to do in the next revision.

-- [[Main.BrentHahoe][Brent Hayhoe]] - 2013-10-30

One of the things I like in VHDL is its verbosity (I'm odd) and rather than adding more optional syntax, I'd rather take some away thus:
<verbatim>
component identifier is 
  [ local_generic_clause ]
  [ local_port_clause ]
end component [ component_simple_name ] ;</verbatim>

and:
<verbatim>
entity identifier is
  entity_header
  entity_declarative_part
[ begin
  entity_statement_part ]
end entity [ entity_simple_name ] ;</verbatim>

Reluctantly, I've refrained from suggesting that the 'simple_name' should be compulsary also.

I believe the current situation arose from maintaining backward compatability?

My suggestion would break this, but in general, do not most tools handle VHDL version compilation control?

-- [[Main.BrentHahoe][/Brent Hayhoe/]] - 2013-10-30

_Main.RyanHinton - 2014-11-05_ I think consistency is paramount in a programming language. Whenever I work on a colleague's code, I try to maintain their style as much as possible. I completely agree that I rather like VHDL's verbosity, and I have my editor configured to include all the optional keywords because I think they make the code more understandable. The more terse forms can be useful in email discussions and book examples. But most of all I want them to be consistent.

Coming from the (Visual) Basic world: I like &lt;keyword&gt; .... End &lt;keyword&gt; languages.

-- Main.PatrickLehmann - 2016-02-19
---++ Supporters

_-- Main.RyanHinton - 2014-11-05_

-- Main.LievenLemiengre - 2015-06-04

-- Main.PatrickLehmann - 2016-02-19

_Add your signature here to indicate your support for the proposal_
Topic revision: r1 - 2020-02-17 - 15:34:39 - TWikiGuest
P1076