ProtectedTypesPublicSignal < P1076

P1076 Web>Vhdl2019CollectedRequirements>ProtectedTypesPublicSignal (2020-02-17, JimLewis) (raw view)EditAttach

---+ Protected Types with Public Signals

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   * Who Updates: Main.JimLewis, &lt;Add YourName &gt;, ...
   * Date Proposed: 2012-Jan-05
   * Date Last Updated: 2014-Nov-13 (split out from [[ProtectedTypeUpdates]])
   * Priority:
   * Complexity:
   * Focus: Testbench

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---++ Requirement Summary

Allow public signals in a protected type declarative region. Access to these signals shall use a record like dot notation. Values driven from within the protected type are deposit only (similar to private Signal/Event class objects). Values driven from outside the protected type have normal drivers.

Allows protected type to be an abstract communication channel with similar capabilities to an interface in SystemVerilog.

---++ Questions

---++ General Comments

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-- Main.ErnstChristen - 2015-01-27

There are about 6 proposals related to improving the management of ports:
   * [[P1076.BlockInterfaces][Records with Directional Subtypes]]
   * [[P1076.PackageAsInterface][Packages as an interface construct]]
   * [[P1076.InterfaceConstructandPortModeConfigurations][Interface Construct and Port Mode Configurations]]
   * [[P1076.NewBusModeForBidirectionalPortSignals][Add "Bus" mode for bidirectional port signals]]
   * [[P1076.ProtectedTypesPublicSignals][Protected Types with Public Signals]] - This proposal
   * [[P1076.ProtectedTypeEntity][Protected Type on Entity Interface]]

It would be worthwhile to derive generic requirements for port/interface management instead of looking at them in isolation.
---++ Supporters

_Add your signature here to indicate your support for the proposal_

-- Main.JimLewis - 2014-12-03

-- [[Main.BrentHahoe][Brent Hayhoe]] - 2014-12-22

-- Main.MortenZilmer - 2015-01-21

-- Main.PatrickLehmann - 2016-02-19

Topic revision: r7 - 2020-02-17 - 15:34:36 - JimLewis

P1076