ObjectIntrospection < P1076

P1076 Web>Vhdl2019CollectedRequirements>Whiteboards>ObjectIntrospection (2015-07-15, JingPang) (raw view)EditAttach
---+ Object Introspection in VHDL

%TOC%

---++ Proposal Details
   * Who Updates: Jing Pang
   * Date Proposed: 2015-7-15
   * Date Last Updated: 2015-7-15
   * Priority:
   * Complexity:
   * Focus:

---+++ Current Situation

<div id="_mcePaste">VHDL's attribute mechanism provides a introspection capability and provides access to simulation behavior.</div> <div id="_mcePaste">For example, the attribute of 'INSTANCE_NAME provides Hierarchical name of the entity.</div> <div id="_mcePaste">However, the attribute feature of VHDL has limited ability to determine the name and data types of</div> <div id="_mcePaste">data members in an object.</div> <div id="_mcePaste">Using introspection allows one design entity to dynamically dtermaine name and data types values of</div> <div id="_mcePaste">parameters in the design.</div>

---+++ Requirement

Use a method "instanceof" combined with attribute, point and level of hierichy

features for object instrospection.
---+++ Implementation details

Syntax:

1). (intanceof(entity_name)'class_name-&gt;object_name, level_number)

This returns '1' to represent the intropection success.

This returns '0' to represent the intropection failure.

2). (intanceof(entity_name)'class_name-&gt;all, level_number)

This displays all names

Allowed class_name:

port, architecture, signal, process, process_label,

instance_label, function, procedure

Level_number: 0 indicate current top hierarchical level;

1 indicate 1 level lower than the top hierarchical level;

2 indicate 2 levels lower than the top hiearchical level;

etc.
---+++ Code Examples
<pre>Half Adder:     

library ieee;
use      ieee.std_logic_1164.all;

entity ha is 
    port( a, b:  in std_logic;  
             cout, s: out std_logic);
end ha;

architecture dataflow of ha is
begin
          s      &lt;=  a   xor  b;
          cout &lt;=  a  and  b;
end dataflow;


Full Adder:
library ieee;
use      ieee.std_logic_1164.all;

entity fa is 
    port( a, b, cin:  in std_logic;  
             cout, s: out std_logic);
end fa;

architecture fa_beh of fa is
signal  sm, p, q:     std_logic;

component ha 
    port( a, b:      in   std_logic;  
             cout, s: out std_logic);
end component;

begin
         u1:   ha  port map(a=&gt;a,   b=&gt;b,    cout=&gt; p, s=&gt; sm );
         u2:   ha  port map(a=&gt;sm, b=&gt;cin, cout=&gt; q, s=&gt; s );
         cout &lt;= p or q;

end   fa_beh;

Testbench for Full Adder Design:

library ieee;
use      ieee.std_logic_1164.all;

entity test_fa is    
end test_fa;

architecture beh of test_fa is

component fa  
    port( a, b, cin:   in    std_logic;  
             cout, s:    out  std_logic );
end component;

signal  a, b, cin, cout, s:     std_logic;

begin
        uut:   fa  port map( a =&gt; a,  b=&gt; b, cin=&gt; cin, cout =&gt; cout, s=&gt;s);
 
        process
        begin
             a  &lt;= '0';    b&lt;='0';   cin &lt;= '0';
             wait for 10 ns;
        a  &lt;= '0';    b&lt;='0';   cin &lt;= '1';
             wait for 10 ns;
        a  &lt;= '0';    b&lt;='1';   cin &lt;= '0';
             wait for 10 ns;
            
            -- Pseudocodes are shown below
            --$display( intanceof(entity_name)'class_name-&gt;object_name, level_number ) 
            --$display( intanceof(entity_name)'class_name-&gt;all,        level_number )        
            -- Pseudocode 
              $display(intanceof(fa)'port-&gt;a, 1);                --  This resturns '1' to indicate a is a port for full adder
              $display(instanceof(test_fa)'instance_label-&gt;uut, 0);  --  This resturns '1' to indicate uut is an instance label
              $display(instanceof(fa)'port-&gt;all, 1);                          --  This returns all port names of  a, b, cin, cout, s.
             
 
             wait;
        end process;

end beh; 





</pre>
---++ Use Cases

Testbench Simulation, Design Verification, etc.
---++ Arguments FOR

---++ Arguments AGAINST

---++ General Comments

---++ Supporters

_Add your signature here to indicate your support for the proposal_
Attachments
I	Attachment	Action	Size	Date	Who	Comment
txt	Proposal_Sample_7_15_2015.txt	manage	2.2 K	2015-07-15 - 20:13	JingPang
Topic revision: r1 - 2015-07-15 - 20:23:16 - JingPang
P1076