Language Change Specification for Anonymous Types

Details of Language Change

Section 6.5.2 Interface object declarations

[016.1: Edit productions in 6.5.2 and Annex C as follows]

  interface_constant_declaration ::=
    [ constant ] identifier_list : [ in ] subtype_indication interface_type_indication [ := static_expression ]

  interface_signal_declaration ::=
    [ signal ] identifier_list : [ mode ] subtype_indication interface_type_indication [ bus ] [ := static_expression ]

    interface_variable_declaration ::=
    [ variable ] identifier_list : [ mode ] subtype_indication interface_type_indication [ := static_expression ]

  interface_type_indication ::=
    subtype_indication 
    | anonymous_type_indication 

[Editing note: For anonymous type indication see LCS_2016_059

[016.2: Add paragraph in 6.5.2 on page 74 before first paragraph]

[016.3 Add paragraph in 6.5.2 after paragraph]

016.4 [Edit paragraph 3 on page 74 of section 6.5.2]

[016.5 Add list item to paragraph 4 on page 74 of section 6.5.2]

[016.6 Add to end of section 6.5.2 after the last note at the bottom of page 75]

Example:
-- An entity whose type of the formal signal port A is defined by an anonymous type declaration.
entity E is
  port (
    A : type is private ;   -- any type
    B : type is <>          -- a scalar type
  ) ; 

-- The equivalent entity with a formal generic type (here designated
-- as anonymous for clarity) and the signal port A whose type is designated  
-- by the unnamed formal generic type.
entity E is
  generic (
    type Anonymous1 is private ;  -- any type
    type Anonymous2 is <>         -- a scalar type
  )
  port (
    A : Anonymous1 ;
    B : Anonymous2 
  ) ; 

Section 6.5.7.1 General (of Association lists)

[016.7 Add paragraph: In section 6.5.7.1 on page 81 after ...]

For any VHDL construct with a port or parameter association list whose corresponding interface object declaration has a type defined by an anonymous type declaration, there is a corresponding construct with a generic association list and a port or parameter list. For each formal port or parameter whose type is specified as an anonymous type declaration, an association element is added to the end of the generic association list to associate the anonymous formal generic type with the subtype of the actual port or parameter. It is an error if the subtype of the actual port or parameter is not determinable from the context. If a generic association list does not already exist, one is created. The original port or parameter list is unchanged.

[016.8 Add to end of section 6.5.7.1 after the last note at the top of page 85]

Architecture A of E is 
  signal SigA : std_logic_vector(7 downto 0) ; 
  signal SigB : std_logic ; 
  component E is
    port (
      A : type is private ; -- any type
      B : type is <>        -- a scalar type
    ) ; 
  end component E ; 
begin 
  -- A component instance whose type of the formal signal port A is defined by an anonymous type declaration.
  E1 :  E 
    port map (
      A => SigA  ; 
      B => SigB
    ) ; 
    ... 
  
-- The equivalent component declaration and instance.
Architecture A of E is 
  signal SigA : std_logic_vector(7 downto 0) ; 
  signal SigB : std_logic ; 
  -- The equivalent component declaration is formed by the rules of section 6.5.2
  component E is
    generic (
      type Anonymous1 is private ;  -- any type
      type Anonymous2 is <>         -- a scalar type
    )
    port (
      A : Anonymous1 ;
      B : Anonymous2 
    ) ; 
  end component E ; 
begin 
  -- The equivalent component instance has a generic map to associate the 
  -- subtype of actual port SigA with the formal generic type Anonymous.
  -- The component instance has the same port map as the original instance.
  E1 :  E 
    generic map (
      Anonymous1 => SigA'SUBTYPE ;
      Anonymous2 => SigB'SUBTYPE
    )
    port map (
      A => SigA  ; 
      B => SigB
    ) ; 
    ...