LCS2016_016 < P1076

P1076 Web>VHDL2017>LCS2016_016 (2017-07-16, JimLewis) (raw view)EditAttach
---+ Language Change Specification for Anonymous Types

---++ 

 | <sticky><b>LCS Number:</b></sticky> | LCS-2016-016 |
 | <sticky><b>Version:</b>   </sticky> | 5 |
 | <sticky><b>Date:</b>      </sticky> | 21-Mar-2017 |
 | <sticky><b>Status:</b>    </sticky> | Voting |
 | <sticky><b>Author:</b>    </sticky> | Jim Lewis |
 | <sticky><b>Email:</b>     </sticky> | [[Main.JimLewis]] |
 | <sticky><b>Source Doc:</b></sticky> | [[AnonymousTypes][Anonymous Types]] |
 | <sticky><b>More Doc:</b></sticky> | [[LCS2016_016_history][History]] |
 | <sticky><b>Related LCS':</b></sticky> | [[LCS2016_059][Interface Type Declarations - LCS_2016_059]] %BR% \
                                           [[LCS2016_049][Generics on subprogram call - LCS_2016_049]] %BR% \
                                           [[LCS2016_086][All interface lists are ordered - LCS_2016_086]] |
 | <sticky><b>Summary:</b>   </sticky> | Leverages interface type definitions introduced in generic lists to  \
                                         create an anonymous type declaration for interface lists |
                                         

---++ Style Notes
<noautolink><sticky>
Changes are shown in %RED%red font%ENDCOLOR%.  
Deletions are %RED%<del>crossed out</del>%ENDCOLOR%. 
Editing notes in %GREEN%green font%ENDCOLOR%. 
 
---++ Details of Language Change

 
---+++ Section 6.5.2  Interface object declarations
---++++ <font color="green">[016.1: Edit productions in 6.5.2 and Annex C as follows]</font>
<pre>
  interface_constant_declaration ::=
    [ constant ] identifier_list : [ in ] <font color="red"><strike>subtype_indication</strike> interface_type_indication</font> [ := static_expression ]

  interface_signal_declaration ::=
    [ signal ] identifier_list : [ mode ] <font color="red"><strike>subtype_indication</strike> interface_type_indication</font> [ bus ] [ := static_expression ]

    interface_variable_declaration ::=
    [ variable ] identifier_list : [ mode ] <font color="red"><strike>subtype_indication</strike> interface_type_indication</font> [ := static_expression ]

  <font color="red">interface_type_indication ::=
    subtype_indication 
    | anonymous_type_indication 
</font></pre> 

<font color="green">[Editing note:  [[LCS2016_059][For anonymous type indication see  LCS_2016_059]]</font>

---++++ <font color="green">[016.2:  Add paragraph in 6.5.2 on page 74 before first paragraph]</font>
<font color="red">
For any VHDL construct that has formal port or parameter
whose type is specified as an anonymous type declaration, 
there is an equivalent construct with a 
generic list and modified port or parameter list.
For each interface object declaration that contains an 
anonymous type declaration, there is a corresponding anonymous 
formal generic type added to the end of the generic list.
If a generic list does not exist, one is created.
The modified port or parameter list contains the same declarations 
as the original port or parameter list, except that each anonymous 
type declaration is replaced by a reference to the corresponding 
anonymous formal generic type.  
The anonymous formal generic type does not have a simple name. 
</font>

---++++ <font color="green">[016.3  Add paragraph in 6.5.2 after paragraph]</font>
<font color="green">[Note:  this could be put in the section on formal generic types.
However, it is not there and there are corresponding notes in signal and constant.
Hence, it should have always been here too.]</font>%BR%
<font color="red">
For an interface constant, signal, or variable declaration whose subtype indication
is a formal generic type, a check is required that the actual generic type 
complies with the rules for subtype indication for the corresponding interface object.
Depending on the implementation, this check may be done during analysis of the 
instantiation or call, or it may be deferred until the design hierarchy is elaborated.
</font>

---++++ <font color="green">016.4 [Edit paragraph 3 on page 74 of section 6.5.2]</font>
If an interface signal declaration includes the reserved word bus, then the signal 
declared by that interface declaration is a guarded signal of signal kind bus.
<font color="red">It is an error if an interface signal declaration includes both
an anonymous type declaration and the reserved word bus.</font>

---++++ <font color="green">[016.5  Add list item to paragraph 4 on page 74 of section 6.5.2]</font>
<font color="green">[Edit note:  paragraph shown to help locate list item]</font>
If an interface declaration contains a “:=” symbol followed by an expression, 
the expression is said to be the default expression of the interface object. 
The type of a default expression shall be that of the corresponding
interface object. 
It is an error if a default expression appears in an interface declaration 
and any of the following conditions hold:
   - ... <font color="green">[This LCS does not change the other list elements]</font>%BR%
   - <font color="red">The type of the interface object is specified with an interface type definition</font>%BR%

---++++ <font color="green">[016.6  Add to end of section 6.5.2 after the last note at the bottom of page 75]</font>
<pre><font color="red">
Example:
-- An entity whose type of the formal signal port A is defined by an anonymous type declaration.
entity E is
  port (
    A : type is private ;   -- any type
    B : type is <>          -- a scalar type
  ) ; 

-- The equivalent entity with a formal generic type (here designated
-- as anonymous for clarity) and the signal port A whose type is designated  
-- by the unnamed formal generic type.
entity E is
  generic (
    type Anonymous1 is private ;  -- any type
    type Anonymous2 is <>         -- a scalar type
  )
  port (
    A : Anonymous1 ;
    B : Anonymous2 
  ) ; 
</font></pre>

---+++ Section 6.5.7.1 General (of Association lists)
---++++ <font color="green">[016.7  Add paragraph: In section 6.5.7.1 on page 81 after ...]</font>

<font color="red">
For any VHDL construct with a port or parameter association list whose 
corresponding interface object declaration has a type defined by an 
anonymous type declaration, 
there is a corresponding construct with a generic association list 
and a port or parameter list. 
For each formal port or parameter whose type is specified 
as an anonymous type declaration, 
an association element is added to the end of the generic association list 
to associate the anonymous formal generic type with the 
subtype of the actual port or parameter.  
It is an error if the subtype of the actual port or parameter is not determinable from the context.
If a generic association list does not already exist, one is created.
The original port or parameter list is unchanged. 
</font>


---++++ <font color="green">[016.8 Add to end of section 6.5.7.1 after the last note at the top of page 85]</font>
<font color="red">Example
<pre>Architecture A of E is 
  signal SigA : std_logic_vector(7 downto 0) ; 
  signal SigB : std_logic ; 
  component E is
    port (
      A : type is private ; -- any type
      B : type is <>        -- a scalar type
    ) ; 
  end component E ; 
begin 
  -- A component instance whose type of the formal signal port A is defined by an anonymous type declaration.
  E1 :  E 
    port map (
      A => SigA  ; 
      B => SigB
    ) ; 
    ... 
  
-- The equivalent component declaration and instance.
Architecture A of E is 
  signal SigA : std_logic_vector(7 downto 0) ; 
  signal SigB : std_logic ; 
  -- The equivalent component declaration is formed by the rules of section 6.5.2
  component E is
    generic (
      type Anonymous1 is private ;  -- any type
      type Anonymous2 is <>         -- a scalar type
    )
    port (
      A : Anonymous1 ;
      B : Anonymous2 
    ) ; 
  end component E ; 
begin 
  -- The equivalent component instance has a generic map to associate the 
  -- subtype of actual port SigA with the formal generic type Anonymous.
  -- The component instance has the same port map as the original instance.
  E1 :  E 
    generic map (
      Anonymous1 => SigA'SUBTYPE ;
      Anonymous2 => SigB'SUBTYPE
    )
    port map (
      A => SigA  ; 
      B => SigB
    ) ; 
    ... 

</font></pre>
Topic revision: r25 - 2017-07-16 - 04:04:20 - JimLewis
P1076