(r24) InterfaceAndBundleEnhancements < P1076

P1076 Web>Vhdl2019CollectedRequirements>InterfaceAndBundleEnhancements (revision 24) (raw view)~~EditAttach~~
---+ Interface and Bundle Enhancements

%TOC%

---++ Proposal Details
   * Who Updates: Main.P1076Group
   * Date Proposed: ongoing
   * Date Last Updated:
   * Priority:
   * Complexity:
   * Focus:

---+++ Current Situation

We have numerous requests for abstract connections between RTL components as well as testbench components. This proposal intends to extract a unified set of requirements and use modes.

[[InterfaceAcceptedRequirements][Interface requirements documentation]]

[[InterfaceSemanticsDiscussion][Interface Semantics Discussion]]

---+++ Updated Use Cases
   1 [[SpiWithPortViewSpaceShip][SPI implemented with LCS 45 Port View + LCS 70 SpaceShip]]


Bus Master, 4 Slaves with Different Address and Data lengths
   1 [[RobMasterWDecodeMuxEntitySeparateBus][Rob Style:  Bus with Decode and Mux in Separate entity + separate slave busses]]
   1 [[BrentMasterMultiplexerEntity][Brent Style:  Decode/Mux in Master.   Using Entities and Spaceships]]
   1 [[RobMasterWDecodeMuxEntityMap][Rob Style:  Bus with Decode and Mux in Separate entity + 1 general purpose slave bus - using map]]
   1 [[RobMasterWDecodeMuxEntityNull][Rob Style:  Bus with Decode and Mux in Separate entity + 1 general purpose slave bus - using NULL LCS 45 b]]
   1 [[http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/InterfaceConstructandPortModeConfigurations#Analysis][Brent Style:  Decode/Mux in Master Using Generics - Brent's Code]]

---+++ Updated Use Cases that look forward
   1 [[SpiFutureUseCase][SPI Beyond Current LCS']]

---+++ Use Cases
   1 [[UCInterfaceDocTransBasedTB][Interface,doc 3.1.: Transaction Based Testbench]]
   1 [[UCInterfaceDocRTLBundles][Interface.doc 3.2.: RTL Bundles]]
   1 [[UCInterfaceDocRTLSimpleIF][Interface.doc 3.2.: RTL Simple Interface]]
   1 [[UCInterfaceDocCurrentCapab][Interface.doc 4.0.: Current Capabilities]]
   1 [[UCInterfaceDocImplemConsider][Interface.doc 5.0.: Implementation Considerations]]
   1 [[UCInterfaceDocInterfaceImplem][Interface.doc 6.0.: Interface Implementation]]
   1 [[UCInterfaceDocHistoricDiscuss][Interface.doc 7.0.: Historical Discussion]]
   1 [[UCProposalBlockInterfaces][Proposal: Records with Directional Subtypes]]
   1 [[UCProposalNewBusModeForBidirectionalPortSignals][Proposal: "Bus" port mode for bidirectional port signals]]
   1 [[UCProposalInterfaceConstructandPortModeConfigurations][Proposal: Interface Construct and Port Mode Configurations]]
   1 [[UCProposalPackageAsInterface][Proposal: Packages as an Interface Construct]] %BR% [[%ATTACHURL%/package_as_interface.zip][Simulatable example of generic package as interface]] %BR% [[%ATTACHURL%/package_record_as_interface.zip][Simulatable example of regular package as interface with internal record signal - does not use generic pacakges]]
   1 [[UCIR2067LogicalLinkInterfaceAbstraction][IR2067: Logical link interface abstraction]]
   1 [[UCIR2089DirectionalRecords][IR2089: Directional Records]]
   1 [[UCVHDL200xFT17CompositeInterfaceMode][VHDL-200x FT17: Composite interface mode]]
   1 [[UCMinimalRTLSignalInterface][Use Case: Minimal RTL Signal Based Interface]]
   1 [[UCComplexRTLSignalCPUInterface][Use Case: Complex RTL Signal Based CPU Bus Interface]] %BR% [[%ATTACHURL%/ComplexRTL.tar.gz][Compressed tarball with VHDL files]]
   1 [[SpiExample][SPI Example]] %BR% [[%ATTACHURL%/SPI_Bus.tar.gz][Compressed tarball with VHDL files]] %BR% [[%ATTACHURL%/SimpleSpi.zip][Simple SPI simulation model using record signal in package (emulating the interface)]]

---+++ Requirements

   1 RTL Requirements- Light Weight -
      1 Must be synthesis capable
      1 Composite/Collection of objects
         * *signal* - required
      1 Create by declation, instantiation, ...
      1 Method to access elements/subelements that is independent of method or location of declaration
      1 Declare / specify on entity interface or subprogram interface
      1 Associate/Map on entity instance or subprogram call
      1 ?Generics
      1 Method for sizing unconstrained elements
      1 ?Support Shared Globals (Clk, Reset, ...) - similar to SV interfaces
         1 How do we handle globals like clk and reset? How does this impact events?
      1 Events - do we care whether events are on individual objects or as a composite
         1 What does event mean if the object is out mode?
         1 What about a collection of clocks?
         1 What about a collection of busses?
      1 Assignment to entire collection? TBD
         1 What if modes/directions are not all out or inout
         1 Would need use cases to validate if all out or inout is useful
         1 ?No because then a record could be used instead
      1 Composition
         1 Collecting other collections
         1 Collecting other modes
         1 ?Shared Globals (Clk, reset, ...)
      1 Access Control / Decomposition - similar to !ModPort
         1 Direction control of objects
         1 support conjugate and monitor (all in) capability (via attribute or other)
         1 ?Shared Globals (Clk, reset, ...)
         1 ??Access to Subprograms
         1 ??Exclusion of objects
         1 Must support a access control/Decomposition declaration/specification
         1 ?Can access control happen directly on interface?
      1 Decomposition within a program (architecture / procedure)
         1 Assign to items of the collection
         1 Read individual items of the collection
      1 ??Subprograms
   1 *Behavioral Requirements*
      1 Composite/Collection of objects
         * *signal* - required
         * *shared variable* - required (???regular variables???)
         * *constant* - ???
         * *file* - ???
         * *terminal* - required - (VHDL-AMS)
         * *quantity* - required - (VHDL-AMS)
         * *bundle* - required
      1 Create by declation, instantiation, ...
      1 Method to access elements/subelements that is independent of method or location of declaration
      1 Declare / specify on entity interface or subprogram interface
      1 Associate/Map on entity instance or subprogram call
      1 Support Generics
      1 Method for sizing unconstrained elements
      1 Support Shared Globals (Clk, Reset, ...) - similar to SV interfaces
         1 How to handle globals like clk and reset?
      1 Events - want events on individual objects
         1 What does event mean if the object is out mode?
         1 What about a collection of clocks?
         1 What about a collection of busses?
      1 Assignment? Only to elements within the collection
      1 Composition
         1 Collecting other collections
         1 Collecting other modes
         1 Shared Globals
      1 Access Control / Decomposition - similar to !ModPort
         1 Directions of objects
         1 support conjugate and monitor (all in) capability (via attribute or other)
         1 ?Shared Globals (Clk, reset, ...)
         1 ?Access to Subprograms
         1 ???Import/Export of subprograms - big change -
            1 impure subprograms need to access ports of a local entity
         1 Exclusion of objects
         1 Must support a access control/Decomposition declaration/specification
         1 ?Can access control happen directly on interface?
      1 Decomposition within a program (architecture / procedure)
         1 Assign to items of the collection
         1 Read individual items of the collection
      1 Subprograms
         1 access interface internals
      1 Avoid compiler issues when integrating <br />port ( A : !MyMode !MyType) ; -- VHDL already has this in some areas.<br /> port ( A : &lt;MyMode&gt; !MyType) ; -- A fix, but there are many variations<br /> port ( A : !MyType(!MyMode)) ; -- A fix, but there are many variations
      1 Internal to a model, use an identifier to dynamically associate with one of 2 identical interfaces
      1 Virtual Interface
         1 Change interface instance
         1 Dynamically plug in a different testbench

---+++ Active Proposals
   1 [[UCComplexRTLSignalCPUInterface][Use Case: Complex RTL Signal Based CPU Bus Interface]] %BR% [[%ATTACHURL%/ComplexRTL.tar.gz][Compressed tarball with VHDL files]]
   1 [[SpiExample][SPI Example]] %BR% [[%ATTACHURL%/SPI_Bus.tar.gz][Compressed tarball with VHDL files]] %BR%
   1 [[PortGroupsProposal][Port groups proposal]] (deprecated)
   1 [[UCProposalPackageAsInterface][Proposal: Packages as an Interface Construct]] %BR% [[%ATTACHURL%/package_as_interface.zip][Simulatable example of generic package as interface]] %BR% [[%ATTACHURL%/package_record_as_interface.zip][Simulatable example of regular package as interface with internal record signal - does not use generic pacakges]]
   1 [[HeterogeneousInterfaces][Heterogeneous Interfaces]]
   1 [[BundlesProposal][Bundles proposal]]
   1 [[VHDL201xInterfaceImplementationProposal][The Bundle as an Object Alternative]]
   1 [[PortViews][Port views]]

---+++ Older Whiteboard Stuff

[[Whiteboards][Old Whiteboards for brainstorming Proposals & Requirements]]
---+++ Implementation Candidates

[[RecordTypeAnalysis][Analysis of creating an interface capability based on record types]]
---++ Arguments FOR

---++ Arguments AGAINST

---++ General Comments
---+++ Reference Links
---++++ Ernst's Proposal Related Documents
   * [[HeterogeneousInterfaces][Heterogeneous Interfaces]]
   * [[HeterogeneousInterfaceRequirements][Heterogeneous Interface Requirements]]
   * [[SVInterfaces][Overview of SystemVerilog Interfaces]]
   * [[BundlesInVHDL][Bundles in VHDL]]
      * [[BrentHayhoeSimpleRecordBasedBundle][Brent Hayhoe: Comments]]
      * [[DanielKhoSimpleRecordBasedBundle][Daniel Kho: Comments]]
   * [[MovingForward][Status Quo and Moving Forward]]

---++++ Brent Summaries:
   * [[InterfaceConcepts][Interface Mode Requirements]]
   * [[InterfaceBundles][Interface Bundle Requirements]]

---++++ Proposals:
| *Item*  | *Who*  | *Status*  | *Last Modified* | *Description*  | *Supporters Priority* ||
| [[InterfaceAttributes][Interfaces: Attributes for Interfaces]] | Main.JohnAasen | | | Provide attributes for common derived interfaces | ||
| [[BlockInterfaces][Interfaces: Records with Directional Subtypes]]  | Main.PeterFlake  | | | | ||
| [[PackageAsInterface][Interfaces: Packages as an Interface Construct]] | Main.JimLewis | | | | ||
| [[InterfaceConstructandPortModeConfigurations][Interface Construct and Port Mode Configurations]] | [[Main.BrentHahoe][Brent Hayhoe]] | RFC | | Define a new Interface construct for use with composite types and a new Port Mode Configuration concept to provide customizable and hierarchical port modes | ||
| [[NewBusModeForBidirectionalPortSignals][Interfaces: Add "Bus" mode for bidirectional port signals]] | Main.BrianDrummond | RFC | | "Bus" mode on a record port allows different direction for each record member | ||
| [[HeterogeneousInterfaces][Interfaces: Heterogeneous Interfaces in VHDL]] | Main.ErnstChristen | RFC | 2015-11-05 | Define an interface concept as a collection of objects. This makes it possible to give each signal element of an interface different modes without breaking backward compatibility. A port view concept allows a subset of an interface to be made available in a design unit. | ||
   * 
      * [[http://www.eda.org/twiki/bin/view.cgi/P1076/ProtectedTypesPublicSignal][Protected Types with Public Signals]] - [[main.JimLewis][Jim Lewis]]
      * [[http://www.eda.org/twiki/bin/view.cgi/P1076/ProtectedTypeEntity][Protected Type: Shared Variables On Entity Interface]] - [[main.JimLewis][Jim Lewis]]
      * [[http://www.eda.org/twiki/bin/view.cgi/P1076/RecordIntrospection][Record Introspection]] - [[main.ChrisHiggs][Chris Higgs]]
      * [[http://www.eda.org/twiki/bin/view.cgi/P1076/RecordMemberAttribute][Record Introspection & Indexing]] - [[main.BrentHahoe][Brent Hayhoe]]
      * [[http://www.eda.org/twiki/bin/view.cgi/P1076/GenericTypes][Generics on Protected Types]] - [[main.JimLewis][Jim Lewis]]
      * [[http://www.eda.org/isac/IRs-VHDL-2002/IR2067.txt][IR2067 - Logical link interface abstraction]] - Martin Trautmann, analyzed: [[main.PeterAshenden][Peter Ashenden]]
      * [[http://www.eda.org/isac/IRs-VHDL-2002/IR2076.txt][IR2076 - a member attribute for records]] - Rickard Norberg
      * [[http://www.eda.org/isac/IRs-VHDL-2002/IR2089.txt][IR2089 - Directional Records]] - Andreas Doering, never analyzed
      * [[http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/ft17_composite_interface_mode.txt][IEEE 200X FT-17 - Composite interface mode]] - [[main.JimLewis][Jim Lewis]]
      * [[http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/ft14_composites_with_unconstrained_arrays.pdf][IEEE 200X FT-14 & FT-15 - Arrays of unconstrained arrays and records with unconstrained arrays]] - [[main.RyanHinton][Ryan Hinton]]

---++++ Documents:
   * 
      * [[http://www.eda.org/vasg/docs/suave-descr-july-1999.pdf][SUAVE Language Description]] - [[main.PeterAshenden][Peter Ashenden]]
      * [[http://www.eda.org/vasg/docs/Interfaces.pdf][Interfaces]] - [[main.JimLewis][Jim Lewis]]
      * [[http://www.eda.org/vasg/docs/ESC-WP-012-oo-revisited-Rev-1_peter_ashenden.pdf][Object Orientation Revisited]] - [[main.PeterAshenden][Peter Ashenden]]

---++++ Email threads:
   * 
      * [[http://www.eda.org/vhdl-200x/hm/0504.html][vhdl-200x: Requirements for VHDL Interfaces]]
      * [[http://www.eda.org/vhdl-200x/hm/0518.html][vhdl-200x: Requirements for Interfaces]]
      * [[http://www.eda.org/vhdl-200x/hm/0522.html][vhdl-200x: Re: Requirements for Interfaces, Part 1]]
      * [[http://www.eda.org/vhdl-200x/hm/0525.html][vhdl-200x: Re: Requirements for Interfaces, Part 2]]
      * [[http://www.eda.org/vhdl-200x/hm/1296.html][ VHDL Interfaces (was RE: EXTERNAL: Re: vhdl-200x: VHDL enhancements wish list)]]
      * [[http://www.eda.org/vhdl-200x/hm/1677.html][vhdl-200x: Directional records proposal]]
      * [[http://www.eda.org/vhdl-200x/hm/1764.html][{Disarmed} Re: vhdl-200x: Directional records proposal]]
      * [[http://www.eda.org/vhdl-200x/hm/1771.html][vhdl-200x: Records with diectional subtypes]]
      * [[http://www.eda.org/vhdl-200x/hm/2566.html][vhdl-200x: Interfaces with normal, conjugated and monitor flavours]]

---++ Supporters

_Add your signature here to indicate your support for the proposal_

---+ Comments

These points are what I expect from this proposal (as a minimum) in order to support RTL design implementation:
   * At present (VHDL 2008), an interface bus can be encapsulated in a single VHDL object of class *signal* or *variable* associated with a composite type(s).
   * Missing is the ability to pass this VHDL object as a single *port/parameter* association through the interface of an *entity*, and/or a *component*, and/or a *block*, and/or a *procedure*:
      * This can be achieved using the proposed new directional constructs of *record/array* *view*, *port* *view*, or *mode* *view*.
      * These new constructs, as well as defining the interface mode on an element by element basis, must have the ability to explicitly declare an element as disconnected functionally across the *port/parameter* interface whilst maintaining the composite subtype structure. This can be achieved using the proposed new mode type of *null*.
         * The actual of a *port/parameter* interface element of mode *null* has no driver or initial value for the connected object.
         * The formal of a *port/parameter* interface element of mode *null* cannot be read (unless it has an initial value associated with it) or driven and it is an error if otherwise attempted.
         * The purpose of a *port/parameter* interface element of mode *null* is to explicitly show the functional disconnection of the element from its composite *port/ parameter* interface.
      * These disconnected elements also require the ability to be controlled via *generic* constants as part of the new *view* construct.

-- %BUBBLESIG{BrentHahoe - 2016-09-20}%
%COMMENT%
Attachments
I	Attachment	Action	Size	Date	Who	Comment
gz	ComplexRTL.tar.gz	manage	4.4 K	2015-10-16 - 00:23	ErnstChristen	Code related to Complex RTL use case
gz	SPI_Bus.tar.gz	manage	3.4 K	2015-10-16 - 00:22	ErnstChristen	Code related to SPI bus use case
zip	SimpleSpi.zip	manage	4.9 K	2015-10-22 - 05:56	JimLewis	Simple SPI inteface using record signal in package
zip	package_as_interface.zip	manage	11.1 K	2015-10-22 - 01:20	JimLewis	Simulatable example for package as inteface
zip	package_record_as_interface.zip	manage	11.6 K	2015-10-22 - 01:50	JimLewis	Simulatable example for package with record signals as inteface
Topic revision: r1 - 2020-02-17 - 15:34:34 - TWikiGuest
P1076