DanielKhosRawProposals(TODOregroup) < P1076

P1076 Web>Vhdl2019CollectedRequirements>RequirementsDetailTemplate>DanielKhosRawProposals(TODOregroup) (2016-07-13, DanielKho) (raw view)EditAttach
---+ Subprograms

## Single syntax for functions and procedures to do without declaration and definition regions. E.g.:

<verbatim>package subs is end package subs;

package body subs is begin
    function "&"(a, b: std_ulogic) return std_ulogic_vector is begin
        return a & b;
    end function "&";
end package body subs;</verbatim>

This is equivalent to the following:
<verbatim>package subs is
    function "&"(a, b: std_ulogic) return std_ulogic_vector;
end package subs;

package body subs is begin    
    function "&"(a, b: std_ulogic) return std_ulogic_vector is begin
        return a & b;
    end function "&";
end package body subs;</verbatim>

--------------------------------------------------------------------------------------

---+ std.standard

Provide unresolved versions of these types:

## Boolean, bit, integer, character, real, time, and vectors of these

E.g.:

<verbatim>package standard is
    /* IEEE Proposed:
        Unresolved types.
    */
    type unresolved_boolean is ('X',false,true);
    type unresolved_bit     is ('X','0','1');

    /* TODO Add undefined values. */
    --type unresolved_integer is (range -2147483648 to 2147483647, undefined);
    type unresolved_integer is range -2147483648    to 2147483647;

    type unresolved_real    is range -1.0e308       to 1.0e308;
    type unresolved_time    is range -2147483647    to 2147483647
        units
            fs;
            ps  = 1000 fs;
            ns  = 1000 ps;
            us  = 1000 ns;
            ms  = 1000 us;
            sec = 1000 ms;
            min = 60 sec;
            hr  = 60 min;
        end units;

    alias u_boolean is unresolved_boolean;
    alias u_bit     is unresolved_bit;
    alias u_integer is unresolved_integer;
    alias u_real    is unresolved_real;
    alias u_time    is unresolved_time;

    subtype natural     is u_integer range 0 to u_integer'high;
    subtype positive    is u_integer range 1 to u_integer'high;

    type u_boolean_vector   is array(integer range <>) of u_boolean;
    type u_bit_vector       is array(integer range <>) of u_bit;
    type u_integer_vector   is array(integer range <>) of u_integer;
    type u_real_vector      is array(integer range <>) of u_real;
    type u_time_vector      is array(integer range <>) of u_time;

    subtype boolean         is resolved u_boolean;
    subtype bit             is resolved u_bit;
    subtype integer         is resolved u_integer;
    subtype real            is resolved u_real;
    subtype time            is resolved u_time;

    subtype boolean_vector  is (resolved) u_boolean_vector;
    subtype bit_vector      is (resolved) u_bit_vector;
    subtype integer_vector  is (resolved) u_integer_vector;
    subtype real_vector     is (resolved) u_real_vector;
    subtype time_vector     is (resolved) u_time_vector;

    type byte               is array(7 downto 0)        of bit;
    type byte_vector        is array(natural range <>)  of byte;

    type signed_vector      is array(natural range <>)  of signed;
    type unsigned_vector    is array(natural range <>)  of unsigned;
end package standard;


</verbatim>

---+ ieee.std_logic_1164

## TODO

<br /><br />-- %USERSIG{DanielKho - 2016-07-13}%<br /><br />
---++ Comments

<br />External links to these examples will be provided later for easy download and review. -- Main.DanielKho - 2016-07-13

%COMMENT%
Topic revision: r1 - 2016-07-13 - 07:53:01 - DanielKho
P1076