Zero delay ordering of Clocks vs. Data signals

Recommendation: Reject

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General Comments

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• Original VHDL-200X Simulation Performance Reflector Archive

From: Peter Flake (Thu Jan 03 2013 - 09:48:21 PST)

Perf 7: Zero-delay ordering of signals

It is unclear what algorithm is required here. It must cope with multiple clock domains and asynchronous circuits.

From: Brent Hayhoe (Mon Jan 21 2013 - 13:09:26 PST)

PERF-07 Zero-delay ordering of signals

I am presuming that this is to do with clock edges arriving too late (in terms of deltas) with respect to data.

Due to zero delay buffers in the gate level design, they can arrive after the data (from the test bench) rather than just before.

It is an inconvenience, but something which can be worked around. I just add a delta delay loop on the clock in the test bench, which adds as many delta delay cycles to the clock as is required to match the delay in the design.

Having said this, I haven't come across this problem for along time, but then again I don't do many zero delay gate-level simulations either.

My example:

      ---------------------------------------------------------
     |
     | Test Bench          ------------------------------------
     |                    |
     |   CLK              |    |\     |\     |\     |\
     | --->------ ----->--|----| >----| >----| >----| >---
     |           |        |    |/     |/     |/     |/    |
     |        -------     |                               |
     |       | delta |    |     ------<-------------<-----
     |       | delay |    |    |
     |       |  loop |    |    v
     |        -------     |    |          Gate-Level Design
     |           |        |    |
     |          -v-       |   -v-
     |  DATA   |   |      |  |   |
     | --->----|   |--->--|--|   |-------
     |         |   |      |  |   |
     |          ---       |   ---
     |                    |

Where the 'delta delay loop' code is something like:

    signal clk_vs : Std_Logic_Vector(MAX_jg - 1 downto 0);
  begin
    clk_vs(0) <= clk_i;
    for I_jlv 0 to MAX_jg - 2
      loop
      clk_vs(I_jlv + 1) <= clk_vs(I_jlv);
    end loop
    clk_b <= clk_vs(MAX_jg);