WaitLevel < P1076/Ballots

P1076/Ballots Web>Vhdl2019CollectedRequirements>WaitLevel (2020-02-17, JimLewis) (raw view)EditAttach

---+ Level Sensitive Wait

%TOC%

---++ Proposal Information
   * Current Owner: Main.JimLewis, ...
   * Contributors: Main.JimLewis, ...
   * Date Proposed: 2014-June-22
   * Date Last Updated: 2014-June-22
   * Priority:
   * Complexity:
   * Focus: Testbench
   * Related Issues: None
   * Competing Issues: None
---++ Requirement Summary

Level Sensitive Wait

See ISAC [[http://www.eda.org/isac/IRs-VHDL-2002/IR2108.txt][IR2108]]

The [[WaitRepeat]] proposes modifying the language syntax of the wait statement.

---++ A Code Solution

This can easily be accomplished with the code
<verbatim>
if A /= Level then
  wait until A = Level ;
end if; 
</verbatim>

However, what is being sought is a more concise solution.

---++ Encapsulation with a Procedure

If the following worked, it would be an acceptable solution. However while a signal input to an entity allows expressions with VHDL-2008, a signal input to a parameter of a subprogram does not.
<verbatim>procedure WaitLevel (
  signal condition : in boolean 
) is 
begin
  if not condition then
    wait until condition ;
  end if ; 
end procedure WaitLevel ; 
</verbatim>

General support issues: When an expression is passed as input signal parameter, it would have the default value of the type (here false) until a delta cycle passes. Here that works just fine.

---++ Language Based Solution

TBD.

---++ Comments

-- Main.JimLewis - 2014-06-22 Personally I am not excited about a language based solutoin as it would potentially make the wait statement even more complex.

---+++ Arguments Against

---++ Supporters

Topic revision: r4 - 2020-02-17 - 15:35:02 - JimLewis

P1076/Ballots