(r2) UCProposalInterfaceConstructandPortModeConfigurations < P1076/Ballots

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---+ Interface Construct and Port Mode Configurations


---++ Implementation details

---+++ Interface Construct:

<p align="left" style="PADDING-LEFT: 30px">interface_declaration ::=</p> <p align="left" style="PADDING-LEFT: 60px"> *interface* identifier *of* <em>composite_</em>subtype_name *is* </p> <p align="left" style="PADDING-LEFT: 90px">interface_declarative_part</p> <p align="left" style="PADDING-LEFT: 60px"> *end interface* [ <em>interface_</em>simple_name ] ;</p>

Apart from port configurations, the interface could contain various decalarations pertaining to the Interface.

At first I thought that the interface should not infer any form of hardware, mainly being used to provide simplified connectivity and functions/procedures used for abstract test monitoring /stimulus of protocols and transactions. However, maybe within the object entity (as opposed to the structural interconnect side) it could be used to generate the interface I/O functions.

---+++ Port Configuration Construct:

<p align="left" style="PADDING-LEFT: 30px">port_configuration_declaration ::=</p> <p align="left" style="PADDING-LEFT: 60px"> *port configuration* identifier *is* </p> <p align="left" style="PADDING-LEFT: 90px">[ <em>formal_</em>generic_clause ]</p> <p align="left" style="PADDING-LEFT: 90px"><em>formal_</em>composite_port_clause</p> <p align="left" style="PADDING-LEFT: 60px"> *end port configuration* [ <em>port_confguration_</em>simple_name] ;</p> <p align="left" style="PADDING-LEFT: 30px">composite_port_clause ::=</p> <p align="left" style="PADDING-LEFT: 60px"> *port* ( composite_port_list ) ;</p> <p align="left" style="PADDING-LEFT: 30px">composite_port_list ::= composite_interface_list</p> <p align="left" style="PADDING-LEFT: 30px">composite_interface_list ::=</p> <p align="left" style="PADDING-LEFT: 60px">composite_interface_element { ; composite_interface_element }</p> <p align="left" style="PADDING-LEFT: 30px">composite_interface_element ::= composite_interface_declaration</p> <p align="left" style="PADDING-LEFT: 30px">composite_interface_declaration ::=</p> <p align="left" style="PADDING-LEFT: 60px"><em>element_</em>identifier_list : composite_mode_declaration ;</p> <p align="left" style="padding-left: 30px;">composite_mode_declaration ::=</p> <p align="left" style="padding-left: 60px;">mode [ := <em>static_</em>expression ]</p>

---+++ Mode Additions

Two new modes and a custom named mode are required as shown:

<p align="left" style="padding-left: 30px;">mode ::= *in* | *out* | *inout* | *buffer* | *linkage* | composite_mode | *null* | custom_mode</p>

---++++!! *Composite* mode

This mode provides a hierarchical mode structure for composite types.

<p align="left" style="padding-left: 30px;">composite_mode ::=</p> <p align="left" style="padding-left: 60px;"> *composite* ( composite_mode_clause )</p>

<p align="left" style="padding-left: 30px;">composite_mode_clause ::= composite_interface_declaration</p>

---++++!! *Null* mode

This mode is required for interface (sub-)connections that are not used within the connected entity. It provides connectivity/termination at the port, but can neither be driven nor read by the entity.

It is used within composite mode structures.

---++++!! Custom mode

This mode provides a custom named mode structure for composite types.

Because procedures don't need to specify a parameter mode (defaulting to 'in') we need a means of disambiguating the custom mode name.

A suggestion is a new attribute 'mode' which will qualify the name as a mode.

<p align="left" style="padding-left: 30px;">custom_mode ::= <strong>mode</strong>'port_configured_composite_mode</p> <p align="left" style="padding-left: 30px;">port_configured_composite_mode::=</p> <p align="left" style="padding-left: 60px;"><em>port_configuration_</em>simple_name [ ( <em>generic_</em>association_list ) ]</p>

---++ Use Cases

A simple CPU Bus example - define stuff in a package first:

---+++!! CPU Bus Package
<sticky><pre><verbatim>
  package CPU_BUS_pkg is

    -- address & data subtypes
    subtype  ADDR_vst          is Std_Logic_Vector(15 downto 0);
    subtype  DATA_vst          is Std_Logic_Vector(15 downto 0);

    -- slave array definitions
    constant SLAVE_MAX_jc       : Positive := 8;
    subtype  SEL_jst           is Natural range SLAVE_MAX_jc-1 downto 0;
    subtype  SEL_vst           is Std_Logic_Vector(SEL_jst);

    -- the interface sub-records and arrays
    type MASTER_r is                      -- Master record
      record
        ADDR_vl : ADDR_vst;               -- Address bus to slave devices
        DATA_vl : DATA_vst;               -- Data bus from master to slave
        WE_l    : Std_Logic;              -- Write enable from master
        SEL_v   : SEL_vst;                -- Slave enables from master

      end record MASTER_r;

    type SLAVE_r is                       -- Slave record
      record
        DATA_vl : DATA_vst;               -- Data bus from slave to master
        ACK_l   : Std_Logic;              -- Acknowledge to master

      end record SLAVE_r;

    type SLAVE_at is
      array(SLAVE_IF_SEL_jst) of SLAVE_r; -- Array of slave return records

    -- the main interface record
    type CPU_BUS_r is                     -- Bus interface record
      record
        MASTER_rl : MASTER_r;           -- Master record to slaves
        SLAVE_al  : SLAVE_at;           -- Array of slave records to master

      end record CPU_BUS_r;

    -- the interface declaration
    interface CPU_BUS_if of CPU_BUS_r is

      -- these configurations define custom modes which can be 
      -- used on a port mapping of a 'CPU_BUS_r' record type

      -- for a master mapping:
      --   the master element (a record) is an output
      --   the slave element (an array) is an input
      port configuration MASTER_pcfg is
        port(
            MASTER_rl : buffer;
            SLAVE_al  : in
          );
      end port configuration MASTER_pcfg;

      -- for a slave mapping:
      --   the master element (a record) is an input
      --   the slave element (an array) is a composite mode
      --     the generic selects the array element to drive as an output
      --     the other array elements are set to null mode (not driven or read)
      port configuration SLAVE_pcfg is
        generic(
            SEL_jg : SEL_jst
          );
        port(
            MASTER_rl : in;
            SLAVE_al  : composite(
              SEL_jg    : buffer;
              others    : null
            )
          );
      end port configuration SLAVE_pcfg;
  end package CPU_BUS_pkg;
</verbatim></pre></sticky>

The interface statement pertains to the given composite type, in this case 'CPU_BUS_r'.

The port configurations define custom port mode declarations for the composite type of the given interface (CPU_BUS_if ).

---+++!! Master entity declaration:

<sticky><pre><verbatim>
  use work.CPU_BUS_pkg.all
  entity MASTER is
    port(
        CLK_i      : in        Std_Logic;
        CPU_BUS_cp : mode'CPU_BUS_if.MASTER_pcfg
                               CPU_BUS_r;  -- Master port to slaves
        RST_i      : in        Std_Logic
      );
  end entity MASTER;
</verbatim></pre></sticky>

The 'master' entity uses the 'master' port configuration to connect to the record (CPU_BUS_r).

The record type (CPU_BUS_r) could be ommited from the port declaration, as the port configurartion constrains the port (CPU_BUS_cp) to be of this type.

---+++!! Slave entity declaration:

<sticky><pre><verbatim>
  use work.CPU_BUS_pkg.all
  entity SLAVE is
    generic(
        SLAVE_SEL_jg : SEL_jst
      );
    port(
        CLK_i      : in        Std_Logic;
        CPU_BUS_cp : mode'CPU_BUS_if.SLAVE_pcfg(
                         SEL_jg => SLAVE_SEL_jg
                       )       CPU_BUS_r;
        RST_i      : in        Std_Logic
      );
  end entity SLAVE;
</verbatim></pre></sticky>

The 'slave' port configuration uses the generic to map to the selected array element of the port configuartion, the others are mapped as 'null' port modes.

As with the master entity decalaration above, the record type (CPU_BUS_r) could be ommited.

---+++!! Master & Slave Instantiations:
<sticky><pre><verbatim>
    signal CLK_s,
           RST_s      : Std_Logic;
    signal CPU_BUS_rs : CPU_BUS_r;

  begin
    MASTER_i0 : MASTER
      port map (
        CLK_i      => CLK_s,
        CPU_BUS_cp => CPU_BUS_rs, 
        RST_i      => RST_s
      );
    SLAVE_i2 : SLAVE
      generic map (
        SLAVE_SEL_jg => 2           -- slave instance 2
      )
      port map (
        CLK_i      => CLK_i,
        CPU_BUS_cp => CPU_BUS_cs,   -- is mapped through to CPU_BUS_cs.SLAVE_al(2)
        RST_i      => RST_i
      );
    SLAVE_i4 : SLAVE
      generic map (
        SLAVE_SEL_jg => 4           -- slave instance 4
      )
      port map (
        CLK_i      => CLK_i,
        CPU_BUS_cp => CPU_BUS_cs,   -- is mapped through to CPU_BUS_cs.SLAVE_al(4)
        RST_i      => RST_i
      );
</verbatim></pre></sticky>

The 'slave' instantiations have the 'select' generics mapped to their respective values. The port configuration generics have already been mapped in the 'slave' entity declaration.
Topic revision: r1 - 2016-11-15 - 18:23:42 - TWikiGuest
P1076/Ballots