UCComplexRTLSignalCPUInterfaceAHBLcode < P1076/Ballots

P1076/Ballots Web>CollectedRequirements>P1076BallotsInterfaceAndBundleEnhancements>UCComplexRTLSignalCPUInterface>UCComplexRTLSignalCPUInterfaceAHBLcode (2016-09-10, BrentHahoe) (raw view)EditAttach
---+!! AHB-Lite Interface

%TOC%

---++ Example Code

<sticky><pre>%BLACK%
   -------------------------------------------
   -- Support Package for AHB-Lite Protocol --
   -------------------------------------------
   <b>library</b> ieee;
   <b>context</b> ieee.ieee_std_context;

   <b>package</b> amba_ahbl_pkg
      <b>generic</b>(
         slaves_max_jg : positive := 3
      );
      <b>is</b>
      <b>constant</b> slaves_total_jc    : positive := slaves_max_jg;     -- individual slaves
      <b>subtype</b>  slaves_total_jrt  <b>is</b> natural <b>range</b> slaves_total_jc <b>downto</b> 1;

      -- AHBL Slave Select bus
      <b>subtype</b>  HSEL_vst          <b>is</b> std_logic_vector(slaves_total_jrt);

      -- AHBL Address bus
      <b>constant</b> HADDR_width_jc     : positive := 32;
      <b>subtype</b>  HADDR_jrt         <b>is</b> natural <b>range</b> HADDR_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HADDR_vst         <b>is</b> std_logic_vector(HADDR_jrt);

      -- AHBL Size control
      <b>constant</b> HSIZE_width_jc     : positive := 3;
      <b>subtype</b>  HSIZE_jrt         <b>is</b> natural <b>range</b> HSIZE_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HSIZE_vst         <b>is</b> std_logic_vector(HSIZE_jrt);

      -- AHBL Burst control
      <b>constant</b> HBURST_width_jc     : positive := 3;
      <b>subtype</b>  HBURST_jrt         <b>is</b> natural <b>range</b> HBURST_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HBURST_vst         <b>is</b> std_logic_vector(HBURST_jrt);

      -- AHBL Protection control
      <b>constant</b> HPROT_width_jc     : positive := 4;
      <b>subtype</b>  HPROT_jrt         <b>is</b> natural <b>range</b> HPROT_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HPROT_vst         <b>is</b> std_logic_vector(HPROT_jrt);

      -- AHBL Transfer Type control
      <b>constant</b> HTRANS_width_jc     : positive := 2;
      <b>subtype</b>  HTRANS_jrt         <b>is</b> natural <b>range</b> HTRANS_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HTRANS_vst         <b>is</b> std_logic_vector(HTRANS_jrt);

      -- AHBL Data bus
      <b>constant</b> HDATA_width_jc     : positive := 32;
      <b>subtype</b>  HDATA_jrt         <b>is</b> natural <b>range</b> HDATA_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HDATA_vst         <b>is</b> std_logic_vector(HDATA_jrt);

      -----------------------------------------------------
      -- Record & Array Types for AMBA AHB-Lite Protocol --
      -----------------------------------------------------
      -- Slave record for AMBA AHB-Lite bus
      <b>type</b> s_amba_ahb_rt <b>is</b> -- AMBA AHBL slave return record
         <b>record</b>
            HREADYOUT_l : std_logic;     -- AHBL transfer complete
            HRESP_l     : std_logic;     -- AHBL transfer response
            HRDATA_vl   : HDATA_vst;     -- AHBL read data bus (32bit)
         <b>end record</b> s_amba_ahb_rt;

      -- Slave array for AMBA AHB-Lite bus
      <b>type</b> s_amba_ahb_at <b>is</b>
         <b>array</b>(slaves_total_jrt)
            <b>of</b> s_amba_ahb_rt;             -- Array of slave return records

      -- Master record for AMBA AHB-Lite bus
      <b>type</b> m_amba_ahb_rt <b>is</b> -- AMBA AHBL master record
         <b>record</b>
            HRESET_nl   : std_logic;     -- AHBL global reset
            HCLK_l      : std_logic;     -- AHBL global clock

            HREADY_l    : std_logic;     -- AHBL transfer complete
            HADDR_vl    : HADDR_vst;     -- AHBL address bus (32bit)
            HWRITE_l    : std_logic;     -- AHBL transfer write/read control
            HSIZE_vl    : HSIZE_vst;     -- AHBL transfer size control (3bit)
            HBURST_vl   : HBURST_vst;    -- AHBL transfer burst control (3bit)
            HPROT_vl    : HPROT_vst;     -- AHBL access protection control (4bit)
            HTRANS_vl   : HTRANS_vst;    -- AHBL transfer type control (2bit)
            HMASTLOCK_l : std_logic;     -- AHBL locked transfer control
            HWDATA_vl   : HDATA_vst;     -- AHBL write data bus (32bit)
         <b>end record</b> m_amba_ahb_rt;

      --------------------------------------------------------
      -- Record & Array Mode Views for AHBL Composite Types --
      --------------------------------------------------------

      -- Mode view only required for master connection - slave connection is
      -- all of mode 'in'.
      -- Decoder and multiplexor function inputs by default are of mode 'in'.
      <b>record view</b> m_amba_ahb_rvw <b>of</b> m_amba_ahb_rt <b>is</b>
         <b>element</b>(
            HRESET_nl   : <b>in</b>     std_logic;
            HCLK_l      : <b>in</b>     std_logic;

            HREADY_l    : <b>in</b>     std_logic;
            HADDR_vl    : <b>out</b>    HADDR_vst;
            HWRITE_l    : <b>out</b>    std_logic;
            HSIZE_vl    : <b>out</b>    HSIZE_vst;
            HBURST_vl   : <b>out</b>    HBURST_vst;
            HPROT_vl    : <b>out</b>    HPROT_vst;
            HTRANS_vl   : <b>out</b>    HTRANS_vst;
            HMASTLOCK_l : <b>out</b>    std_logic;
            HRDATA_vl   : <b>out</b>    HDATA_vst;
         );
      <b>end record view</b> m_amba_ahb_rvw;

      -----------------------------------------
      -- Decoder and Multiplexor Subprograms --
      -----------------------------------------
      -- Slave select decoder function
      <b>function</b> HSEL_decoder_f(;
            m_amba_ahb_ri : m_amba_ahb_rt
         ) <b>return</b> HSEL_vst;

      -- Slave return multiplexor function
      <b>function</b> slave_multiplexor_f(;
            m_amba_ahb_ri : m_amba_ahb_rt;
            s_amba_ahb_ai : s_amba_ahb_at
         ) <b>return</b> s_amba_ahb_rt;

      --------------------------------
      -- Context Clause for Package --
      --------------------------------
      <b>context</b> amba_ahbl_context;
         <b>library</b> ieee;
         <b>context</b> ieee.ieee_std_context;
            <b>use work</b>.amba_ahbl_pkg.all;
      <b>end context</b> amba_ahbl_context;
   <b>end package</b> amba_ahbl_pkg;

   -- A package body is required to define the decoder and multiplexor
   -- functions.
   <b>package body</b> amba_ahbl_pkg;
      -----------------------------------------
      -- Decoder and Multiplexor Subprograms --
      -----------------------------------------
      -- Slave select decoder function
      <b>function</b> HSEL_decoder_f(;
            m_amba_ahb_ri : m_amba_ahb_rt
         ) <b>return</b> HSEL_vst <b>is</b>
         <b>variable</b> HSEL_vv : HSEL_vst;
      <b>begin</b>
         ...
         <b>return</b> HSEL_vv;
      <b>end function</b> HSEL_decoder_f;

      -- Slave return multiplexor function
      <b>function</b> slave_multiplexor_f(;
            m_amba_ahb_ri : m_amba_ahb_rt;
            s_amba_ahb_ai : s_amba_ahb_at
         ) <b>return</b> s_amba_ahb_rt <b>is</b>
         <b>variable</b> s_amba_ahb_rv : s_amba_ahb_rt;
      <b>begin</b>
         ...
         <b>return</b> s_amba_ahb_rv;
      <b>end function</b> HSEL_decode_f;
   <b>end package body</b> amba_ahbl_pkg;

   -----------------------------------------------------------------
   -- Declare entities for AHBL Master, Slave and top-level Block --
   -----------------------------------------------------------------
   -- AHB-Lite Master Entity
   <b>context work</b>.amba_ahbl_context;
   <b>entity</b> ahbl_master_ent <b>is</b>(
      <b>port</b>(
         s_amba_ahb_ri  : <b>in</b>     s_amba_ahb_rt;
         m_amba_ahb_rif : <b>view</b>   m_amba_ahb_rt(m_amba_ahb_rvw)
      );
   <b>end entity</b> ahbl_master_ent;
   <b>architecture</b> rtl_arch <b>of</b> ahbl_master_ent <b>is</b>
   <b>begin</b>(
      ....
   <b>end architecture</b> rtl_arch;</b>

   -- AHB-Lite Slave Entity
   <b>context work</b>.amba_ahbl_context;
   <b>entity</b> ahbl_slave_ent <b>is</b>(
      <b>port</b>(
         HSEL_i        : <b>in</b>     std_logic;
         m_amba_ahb_ri : <b>in</b>     m_amba_ahb_rt;
         s_amba_ahb_ro : <b>out</b>    s_amba_ahb_rt
      );
   <b>end entity</b> ahbl_slave_ent;
   <b>architecture</b> rtl_arch <b>of</b> ahbl_slave_ent <b>is</b>
   <b>begin</b>(
      ....
   <b>end architecture</b> rtl_arch;</b>

   ---------------
   -- Top Level --
   ---------------
   -- Top-level AHB-Lite Block Structure
   <b>context work</b>.amba_ahbl_context;
   <b>entity</b> ahbl_block_ent <b>is</b>(
   <b>end entity</b> ahbl_block_ent;

   <b>architecture</b> rtl_arch <b>of</b> ahbl_block_ent <b>is</b>
      <b>signal</b> m_amba_ahb_rs : m_amba_ahb_rt;
      <b>signal</b> HSEL_vs       : HSEL_vst;
      <b>signal</b> s_amba_ahb_rs : s_amba_ahb_rt;
      <b>signal</b> s_amba_ahb_as : s_amba_ahb_at;
   <b>begin</b>(

      -- Clock and Reset Control for AHB-Lite Block
      clk_and_rst_inst : <b>entity</b> clk_and_rst_ent(rtl_arch)
         <b>port map</b>(
            rst_o => m_amba_ahb_rs.HRESET_nl,
            clk_o => m_amba_ahb_rs.HCLK_l
         );

      -- Master Instantiation for AHB-Lite Block
      ahbl_master_inst : <b>entity</b> ahbl_master_ent(rtl_arch)
         <b>port map</b>(
            s_amba_ahb_ri  => s_amba_ahb_rs,
            m_amba_ahb_rif => m_amba_ahb_rs
         );

      -- Slave Decoder
      HSEL_decoder_asgn :
         HSEL_vs                <= HSEL_decoder_f(m_amba_ahb_rs);

      -- Slave Multiplexor
      slave_multiplexor_asgn :
         s_amba_ahb_rs          <= slave_multiplexor_f(m_amba_ahb_rs, s_amba_ahb_as);

      -- HREADY decode
      HREADY_asgn :
         m_amba_ahb_rs.HREADY_l <= s_amba_ahb_rs.HREADYOUT_l;

      -- Slave Instantiations for AHB-Lite Block
      ahbl_slave3_inst : <b>entity</b> ahbl_slave_ent(rtl_arch)
         <b>port map</b>(
            HSEL_i        => HSEL_vs(3),
            m_amba_ahb_ri => m_amba_ahb_rs,
            s_amba_ahb_ro => s_amba_ahb_as(3)
         );
      ahbl_slave2_inst : <b>entity</b> ahbl_slave_ent(rtl_arch)
         <b>port map</b>(
            HSEL_i        => HSEL_vs(2),
            m_amba_ahb_ri => m_amba_ahb_rs,
            s_amba_ahb_ro => s_amba_ahb_as(2)
         );
      ahbl_slave1_inst : <b>entity</b> ahbl_slave_ent(rtl_arch)
         <b>port map</b>(
            HSEL_i        => HSEL_vs(1),
            m_amba_ahb_ri => m_amba_ahb_rs,
            s_amba_ahb_ro => s_amba_ahb_as(1)
         );
   <b>end architecture</b> rtl_arch;
%ENDCOLOR%</pre></sticky>

---++ Interface Connections

| *Control Instance:* ||
| clk_and_rst_inst    ||
| *Name*              | *I/O Element*                         | *Mode*        | *Composite Signal or Element* |
| <b>HRESETn</b>      | rst_o                                 | <b>out</b>    | m_amba_ahb_rs.HRESET_nl |
| <b>HCLK</b>         | clk_o                                 | <b>out</b>    | m_amba_ahb_rs.HCLK_l |
| ||||
| *Master Instance:*  ||
| ahbl_master_inst    ||
| *Name*              | *I/O Element*                         | *Mode*        | *Composite Signal or Element* |
| <b>HREADYOUT</b>    | s_amba_ahb_ri.HREADYOUT_l             | <b>in</b>     | s_amba_ahb_rs.HREADYOUT_l |
| <b>HRESP</b>        | s_amba_ahb_ri.HRESP_l                 | <b>in</b>     | s_amba_ahb_rs.HRESP_l |
| <b>HRDATA[31:0]</b> | s_amba_ahb_ri.HRDATA_vl(31 downto 0)  | <b>in</b>     | s_amba_ahb_rs.HRDATA_vl(31 downto 0) |
| ||||
| <b>HRESETn</b>      | m_amba_ahb_rif.HRESET_nl              | <b>in</b>     | m_amba_ahb_rs.HRESET_nl |
| <b>HCLK</b>         | m_amba_ahb_rif.HCLK_l                 | <b>in</b>     | m_amba_ahb_rs.HCLK_l |
| <b>HREADY</b>       | m_amba_ahb_rif.HREADY_l               | <b>in</b>     | m_amba_ahb_rs.HREADY_l |
| <b>HADDR[31:0]</b>  | m_amba_ahb_rif.HADDR_vl(31 downto 0)  | <b>out</b>    | m_amba_ahb_rs.HADDR_vl(31 downto 0) |
| <b>HWRITE</b>       | m_amba_ahb_rif.HWRITE_l               | <b>out</b>    | m_amba_ahb_rs.HWRITE_l |
| <b>HSIZE[2:0]</b>   | m_amba_ahb_rif.HSIZE_vl(2 downto 0)   | <b>out</b>    | m_amba_ahb_rs.HSIZE_vl(2 downto 0) |
| <b>HBURST[2:0]</b>  | m_amba_ahb_rif.HBURST_vl(2 downto 0)  | <b>out</b>    | m_amba_ahb_rs.HBURST_vl(2 downto 0) |
| <b>HPROT[3:0]</b>   | m_amba_ahb_rif.HPROT_vl(3 downto 0)   | <b>out</b>    | m_amba_ahb_rs.HPROT_vl(3 downto 0) |
| <b>HTRANS[1:0]</b>  | m_amba_ahb_rif.HTRANS_vl(1 downto 0)  | <b>out</b>    | m_amba_ahb_rs.HTRANS_vl(1 downto 0) |
| <b>HMASTLOCK</b>    | m_amba_ahb_rif.HMASTLOCK_l            | <b>out</b>    | m_amba_ahb_rs.HMASTLOCK_l |
| <b>HWDATA[31:0]</b> | m_amba_ahb_rif.HWDATA_vl(31 downto 0) | <b>out</b>    | m_amba_ahb_rs.HWDATA_vl(31 downto 0) |
| ||||
| *Slave Instances:*  ||
| ahbl_slavex_inst    ||
| *Name*              | *I/O Element*                         | *Mode*        | *Composite Signal or Element* |
| <b>HSEL</b>         | HSEL_i                                | <b>in</b>     | HSEL_vs(x) |
| ||||
| <b>HRESETn</b>      | m_amba_ahb_ri.HRESET_nl               | <b>in</b>     | m_amba_ahb_rs.HRESET_nl |
| <b>HCLK</b>         | m_amba_ahb_ri.HCLK_l                  | <b>in</b>     | m_amba_ahb_rs.HCLK_l |
| <b>HREADY</b>       | m_amba_ahb_ri.HREADY_l                | <b>in</b>     | m_amba_ahb_rs.HREADY_l |
| <b>HADDR[31:0]</b>  | m_amba_ahb_ri.HADDR_vl(31 downto 0)   | <b>in</b>     | m_amba_ahb_rs.HADDR_vl(31 downto 0) |
| <b>HWRITE</b>       | m_amba_ahb_ri.HWRITE_l                | <b>in</b>     | m_amba_ahb_rs.HWRITE_l |
| <b>HSIZE[2:0]</b>   | m_amba_ahb_ri.HSIZE_vl(2 downto 0)    | <b>in</b>     | m_amba_ahb_rs.HSIZE_vl(2 downto 0) |
| <b>HBURST[2:0]</b>  | m_amba_ahb_ri.HBURST_vl(2 downto 0)   | <b>in</b>     | m_amba_ahb_rs.HBURST_vl(2 downto 0) |
| <b>HPROT[3:0]</b>   | m_amba_ahb_ri.HPROT_vl(3 downto 0)    | <b>in</b>     | m_amba_ahb_rs.HPROT_vl(3 downto 0) |
| <b>HTRANS[1:0]</b>  | m_amba_ahb_ri.HTRANS_vl(1 downto 0)   | <b>in</b>     | m_amba_ahb_rs.HTRANS_vl(1 downto 0) |
| <b>HMASTLOCK</b>    | m_amba_ahb_ri.HMASTLOCK_l             | <b>in</b>     | m_amba_ahb_rs.HMASTLOCK_l |
| <b>HWDATA[31:0]</b> | m_amba_ahb_ri.HWDATA_vl(31 downto 0)  | <b>in</b>     | m_amba_ahb_rs.HWDATA_vl(31 downto 0) |
| ||||
| <b>HREADYOUT</b>    | s_amba_ahb_ro.HREADYOUT_l             | <b>out</b>    | s_amba_ahb_as(x).HREADYOUT_l |
| <b>HRESP</b>        | s_amba_ahb_ro.HRESP_l                 | <b>out</b>    | s_amba_ahb_as(x).HRESP_l |
| <b>HRDATA[31:0]</b> | s_amba_ahb_ro.HRDATA_vl(31 downto 0)  | <b>out</b>    | s_amba_ahb_as(x).HRDATA_vl(31 downto 0) |
| ||||
| *Decoder Function:* ||
| HSEL_decoder_asgn   ||
| *Name*              | *Input Element*                       | *Mode*        | *Composite Signal or Element* |
| <b>HRESETn</b>      | m_amba_ahb_ri.HRESET_nl               | <b>in</b>     | m_amba_ahb_rs.HRESET_nl |
| <b>HCLK</b>         | m_amba_ahb_ri.HCLK_l                  | <b>in</b>     | m_amba_ahb_rs.HCLK_l |
| <b>HREADY</b>       | m_amba_ahb_ri.HREADY_l                | <b>in</b>     | m_amba_ahb_rs.HREADY_l |
| <b>HADDR[31:0]</b>  | m_amba_ahb_ri.HADDR_vl(31 downto 0)   | <b>in</b>     | m_amba_ahb_rs.HADDR_vl(31 downto 0) |
| <b>HWRITE</b>       | m_amba_ahb_ri.HWRITE_l                | <b>in</b>     | m_amba_ahb_rs.HWRITE_l |
| <b>HSIZE[2:0]</b>   | m_amba_ahb_ri.HSIZE_vl(2 downto 0)    | <b>in</b>     | m_amba_ahb_rs.HSIZE_vl(2 downto 0) |
| <b>HBURST[2:0]</b>  | m_amba_ahb_ri.HBURST_vl(2 downto 0)   | <b>in</b>     | m_amba_ahb_rs.HBURST_vl(2 downto 0) |
| <b>HPROT[3:0]</b>   | m_amba_ahb_ri.HPROT_vl(3 downto 0)    | <b>in</b>     | m_amba_ahb_rs.HPROT_vl(3 downto 0) |
| <b>HTRANS[1:0]</b>  | m_amba_ahb_ri.HTRANS_vl(1 downto 0)   | <b>in</b>     | m_amba_ahb_rs.HTRANS_vl(1 downto 0) |
| <b>HMASTLOCK</b>    | m_amba_ahb_ri.HMASTLOCK_l             | <b>in</b>     | m_amba_ahb_rs.HMASTLOCK_l |
| <b>HWDATA[31:0]</b> | m_amba_ahb_ri.HWDATA_vl(31 downto 0)  | <b>in</b>     | m_amba_ahb_rs.HWDATA_vl(31 downto 0) |
| ||||
| <b>HSEL[3:1]</b>    |                                       | <b>return</b> | HSEL_vs(3 downto 1) |
| ||||
| *Multiplexor Function:* ||
| slave_multiplexor_asgn  ||
| *Name*              | *Input Element*                       | *Mode*        | *Composite Signal or Element* |
| <b>HRESETn</b>      | m_amba_ahb_ri.HRESET_nl               | <b>in</b>     | m_amba_ahb_rs.HRESET_nl |
| <b>HCLK</b>         | m_amba_ahb_ri.HCLK_l                  | <b>in</b>     | m_amba_ahb_rs.HCLK_l |
| <b>HREADY</b>       | m_amba_ahb_ri.HREADY_l                | <b>in</b>     | m_amba_ahb_rs.HREADY_l |
| <b>HADDR[31:0]</b>  | m_amba_ahb_ri.HADDR_vl(31 downto 0)   | <b>in</b>     | m_amba_ahb_rs.HADDR_vl(31 downto 0) |
| <b>HWRITE</b>       | m_amba_ahb_ri.HWRITE_l                | <b>in</b>     | m_amba_ahb_rs.HWRITE_l |
| <b>HSIZE[2:0]</b>   | m_amba_ahb_ri.HSIZE_vl(2 downto 0)    | <b>in</b>     | m_amba_ahb_rs.HSIZE_vl(2 downto 0) |
| <b>HBURST[2:0]</b>  | m_amba_ahb_ri.HBURST_vl(2 downto 0)   | <b>in</b>     | m_amba_ahb_rs.HBURST_vl(2 downto 0) |
| <b>HPROT[3:0]</b>   | m_amba_ahb_ri.HPROT_vl(3 downto 0)    | <b>in</b>     | m_amba_ahb_rs.HPROT_vl(3 downto 0) |
| <b>HTRANS[1:0]</b>  | m_amba_ahb_ri.HTRANS_vl(1 downto 0)   | <b>in</b>     | m_amba_ahb_rs.HTRANS_vl(1 downto 0) |
| <b>HMASTLOCK</b>    | m_amba_ahb_ri.HMASTLOCK_l             | <b>in</b>     | m_amba_ahb_rs.HMASTLOCK_l |
| <b>HWDATA[31:0]</b> | m_amba_ahb_ri.HWDATA_vl(31 downto 0)  | <b>in</b>     | m_amba_ahb_rs.HWDATA_vl(31 downto 0) |
| ||||
| <b>HREADYOUT</b>    | s_amba_ahb_ai(3 downto 1).HREADYOUT_l             | <b>in</b>     | s_amba_ahb_as(3 downto 1).HREADYOUT_l |
| <b>HRESP</b>        | s_amba_ahb_ai(3 downto 1).HRESP_l                 | <b>in</b>     | s_amba_ahb_as(3 downto 1).HRESP_l |
| <b>HRDATA[31:0]</b> | s_amba_ahb_ai(3 downto 1).HRDATA_vl(31 downto 0)  | <b>in</b>     | s_amba_ahb_as(3 downto 1).HRDATA_vl(31 downto 0) |
| ||||
| <b>HREADYOUT</b>    |                                       | <b>return</b> | s_amba_ahb_rs.HREADYOUT_l |
| <b>HRESP</b>        |                                       | <b>return</b> | s_amba_ahb_rs.HRESP_l |
| <b>HRDATA[31:0]</b> |                                       | <b>return</b> | s_amba_ahb_rs.HRDATA_vl(31 downto 0) |
| ||||

-- %USERSIG{BrentHayhoe - 2016-09-09}%

---+ Comments

%COMMENT%
Topic revision: r6 - 2016-09-10 - 13:12:28 - BrentHahoe
P1076/Ballots