SynthesizableEvent < P1076/Ballots

P1076/Ballots Web>Vhdl2019CollectedRequirements>SynthesizableEvent (2020-02-17, JimLewis) (raw view)EditAttach

---+ Synthesizable 'event Attribute

%TOC%

---++ Proposal Details
   * Who Updates: Main.DanielKho, Main.JimLewis, &lt;Add Main.YourName &gt;
   * Date Proposed: 2015-01-02
   * Date Last Updated:
   * Priority:
   * Complexity:
   * Focus:

---+++ Current Situation

Currently, there is no convenient way of describing dual-edge-triggered flip-flops. Existing implementations rely on working around synthesis tools, or instantiating a vendor-specific DDR IP.

---+++ Requirement

Synthesisable 'event attribute for dual-edge triggers. Synthesis tools can infer DDR blocks or have a dual-edge trigger configuration using multiple flip-flops.

---+++ Implementation details

---+++ Code Examples

Example of 'event attribute used in a dual-edge-triggered flip-flop.

<verbatim>process(clk) is
begin
    if clk'event then
        /* Output q is triggered at both edges of the clk. */
        q<=d;
    end if;
end process;</verbatim>

---++ Use Cases
---++ Arguments FOR

---++ Arguments AGAINST

---++ General Comments

---++ Supporters

_Add your signature here to indicate your support for the proposal_

-- Main.DanielKho - 2015-01-02

-- Main.PatrickLehmann - 2016-02-19

Topic revision: r4 - 2020-02-17 - 15:35:00 - JimLewis

P1076/Ballots