StdulogicResolution < P1076/Ballots

P1076/Ballots Web>Vhdl2019CollectedRequirements>StdulogicResolution (2020-02-17, JimLewis) (raw view)EditAttach
---+ Std_ulogic, Resolved, and '-'

%TOC%

---++ Proposal Information
   * Current Owner: JimLewis, ...
   * Contributors: JimLewis, ...
   * Date Proposed: 2014-June-19
   * Date Last Updated: 2014-June-19
   * Priority: low
   * Complexity:
   * Backward Compatibility: Maybe problematic
   * Focus: Testbench
   * Related Issues: None
   * Competing Issues: None
---++ Requirement Summary

Resolution of '-' and 'Z' is 'X", ok for RTL, but bad is for testbenches that use records as interfaces and want to indicate that a field to be checked is a don't care as opposed to a specific value.

See ISAC [[http://www.eda.org/isac/IRs-VHDL-2002/IR2125.txt][IR2125]]

---++ Current Definition of the resolution table
<verbatim>
  constant resolution_table : stdlogic_table := (
    --      ---------------------------------------------------------
    --      |  U    X    0    1    Z    W    L    H    -        |   |  
    --      ---------------------------------------------------------
             ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'),  -- | U |
             ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'),  -- | X |
             ('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'),  -- | 0 |
             ('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'),  -- | 1 |
             ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'),  -- | Z |
             ('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'),  -- | W |
             ('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'),  -- | L |
             ('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'),  -- | H |
             ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X')   -- | - |
             );
</verbatim>

---++ Proposed changes to the resolution table
<verbatim>
  constant resolution_table : stdlogic_table := (
    --      ---------------------------------------------------------
    --      |  U    X    0    1    Z    W    L    H    -        |   |  
    --      ---------------------------------------------------------
             ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'),  -- | U |
             ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'),  -- | X |
             ('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'),  -- | 0 |
             ('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'),  -- | 1 |
             ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'),  -- | Z |
             ('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'),  -- | W |
             ('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'),  -- | L |
             ('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'),  -- | H |
             ('U', 'X', 'X', 'X', '-', 'X', 'X', 'X', 'X')   -- | - |
             );
</verbatim>
---++ Concerns: Backward compatibility

Although this is a simple subtle change, there is a risk of backward compatibility issues.
---++ Alternate Solution

Add a separte resolution function that uses the proposed resolution table in either std_logic_1164 or a user defined/open source package. Generally

<verbatim>
constant resolution_dash_table : stdlogic_table := (
    --      ---------------------------------------------------------
    --      |  U    X    0    1    Z    W    L    H    -        |   |  
    --      ---------------------------------------------------------
             ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'),  -- | U |
             ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'),  -- | X |
             ('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'),  -- | 0 |
             ('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'),  -- | 1 |
             ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'),  -- | Z |
             ('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'),  -- | W |
             ('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'),  -- | L |
             ('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'),  -- | H |
             ('U', 'X', 'X', 'X', '-', 'X', 'X', 'X', 'X')   -- | - |
             );

function resolved_dash (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is 
  variable result : STD_ULOGIC := 'Z'; -- weakest state default 
begin 
-- simplified since resolving 'Z' and '-' is correct! 
  for i in s'range loop 
    result := resolution_dash_table(result, s(i)); 
  end loop; return result; 
end function resolved_dash; 
</verbatim>

Then use it with either std_ulogic or std_ulogic_vector:
<verbatim>
type InterfaceRecType is record
  A_logic : resolved_dash std_ulogic ; 
  B_vector : (resolved_dash) std_ulogic_vector ; 
end record InterfaceRecType ; 
</verbatim>

---++ Comments

The "Alternate Solution" is simple enough that an open source package that includes the resolution function should provide a reasonable implementation.

---+++ Arguments Against

---++ Supporters

-- Main.JimLewis - 2014-06-19 -- Support "Alternate Solution" in an open source package

-- Main.MartinThompson - 2014-06-20 -- Support "Alternate Solution" in an open source package
Topic revision: r3 - 2020-02-17 - 15:35:00 - JimLewis
P1076/Ballots